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14.1.2 1/2/4/8 Bpp Color Depth
15
0
11
22
System
Memory
Address
* High byte lane (D[15:8]) data (e.g. 11) is associated with even address.
* Low byte lane (D[7:0]) data (e.g. 22) is associated with odd address.
S1D13706
X31B-A-001-08
For 1/2/4/8 bpp color depth, byte swapping must be performed on the bus data but not the
display data.
For 1/2/4/8 bpp color depth, the Display Data Byte Swap bit (REG[71h] bit 6) must be
set to 0.
D[15:8]
D[7:0]
0
CPU Data
Byte Swap
System
Memory
Display
(Big-Endian)
Buffer
(Little-Endian)
Figure 14-2: Byte-swapping for 1/2/4/8 Bpp
15
0
0
22
11
Epson Research and Development
Vancouver Design Center
Display
Buffer
Address
11 22
Hardware Functional Specification
Issue Date: 01/11/13
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