S1D13706 Hardware Configuration; Memory Mapping And Aliasing - Epson S1D13706 Technical Manual

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4.2 S1D13706 Hardware Configuration

S1D13706
Pin Name
CNF[2:0]
CNF3
CNF4
CNF5
CNF[7:6]

4.3 Memory Mapping and Aliasing

S1D13706
X31B-G-002-02
The S1D13706 latches CNF7 through CNF0 to allow selection of the bus mode and other
configuration data on the rising edge of RESET#. For details on configuration, refer to the
S1D13706 Hardware Functional Specification, document number X31B-A-001-xx.
The table below shows the configuration settings important to the Generic #2 host bus
interface used by the Toshiba TMPR3905/12.
Table 4-1: Summary of Power-On/Reset Configuration Options
value on this pin at the rising edge of RESET# is used to configure: (1/0)
1
100 = Generic #2 Host Bus Interface
GPIO pins as inputs at power on
Big Endian bus interface
Active high WAIT#
see Table 4-2:CLKI to BCLK Divide Selection for recommended setting
= configuration for Toshiba TMPR3905/12 microprocessor
Table 4-2: CLKI to BCLK Divide Selection
CNF7
CNF6
0
0
0
1
1
0
1
1
= recommended setting for TMPR3905/12 microprocessor
In this implementation the TMPR3905/12 control signal CARDREG* is ignored. This
means that the S1D13706 takes up the entire PC Card slot 1.
The S1D13706 is a memory mapped device and uses two 128K byte blocks which are
selected using A17 from the MPC821 (A17 is connected to the S1D13706 M/R# pin). The
internal registers occupy the first 128K bytes block and the 80K byte display buffer
occupies the second 128K byte block.
The registers occupy the range 0h through 1FFFFh while the on-chip display memory
occupies the range 20000h through 3FFFFh. Demultiplexed address lines A[25:18] are
ignored. Therefore, the S1D13706 is aliased 256 times at 256K byte intervals over the 64M
byte PC Card slot #1 memory space.
Note
If aliasing is undesirable, additional decoding circuitry must be added.
GPIO pins as HR-TFT / D-TFT outputs
Little Endian bus interface
Active low WAIT#
CLKI to BCLK Divide
1:1
2:1
3:1
4:1
Interfacing to the Toshiba MIPS TMPR3905/3912 Microprocessors
Epson Research and Development
Vancouver Design Center
0
Issue Date: 01/02/23

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