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Philips Semiconductors
ARM-based Microcontroller
Command Register (CANCMR - 0xE00x x004)
Writing to this write-only register initiates an action. Bits not listed should be written as 0. Reading this register yields zeroes.
See Table 124 for details on specific CAN channel register address.
Table 126: CAN Command Register (CANCMR - 0xE00x x004)
CANCMR Name Function
1: Transmission Request -- the message, previously written to the CANTFI, CANTID, and optionally the
0
TR
CANTDA and CANTDB registers, is queued for transmission.
1: Abort Transmission -- if not already in progress, a pending Transmission Request is cancelled. If this bit
1
AT
and TR are set in the same write operation, frame transmission is attempted once, and no retransmission is
attempted if an error is flagged nor if arbitration is lost.
1: Release Receive Buffer -- the information in the CANRFS, CANRID, and if applicable the CANRDA and
2
RRB
CANRDB registers is released, and becomes eligible for replacement by the next received frame. If the next
received frame is not available, writing this command clears the RBS bit in CANSR.
3
CDO 1: Clear Data Overrun -- The Data Overrun bit in CANSR is cleared.
1: Self Reception Request -- the message, previously written to the CANTFS, CANTID, and optionally the
CANTDA and CANTDB registers, is queued for transmission. This differs from the TR bit above in that the
4
SRR
receiver is not disabled during the transmission, so that it receives the message if its Identifier is recognized
by the Acceptance Filter.
5
STB1 1: Select Tx Buffer 1 for transmission
6
STB2 1: Select Tx Buffer 2 for transmission
7
STB3 1: Select Tx Buffer 3 for transmission
CAN Controllers and Acceptance Filter
LPC2119/2129/2292/2294
193
Preliminary User Manual
May 03, 2004
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