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Philips Semiconductors
ARM-based Microcontroller
Table 2: LPC2119/2129/2194/2292/2294 Registers
Address
Name
Offset
0xE0008028
T1CCR
0xE000802C
T1CR0
0xE0008030
T1CR1
0xE0008034
T1CR2
0xE0008038
T1CR3
0xE000803C T1EMR
UART0
U0RBR
(DLAB=0)
0xE000C000
U0THR
(DLAB=0)
U0DLL
(DLAB=1)
U0IER
(DLAB=0)
0xE000C004
U0DLM
(DLAB=1)
U0IIR
0xE000C008
U0FCR
0xE000C00C U0LCR
Introduction
Description
MSB
4 reserved (-) bits
T1 Capture
Control
Int. on
Int. on
Register
Cpt.2
Cpt.2
falling
rising
T1 Capture
Register 0
T1 Capture
Register 1
T1 Capture
Register 2
T1 Capture
Register 3
4 reserved (-) bits
T1 External
Match
External Match
Register
Control 1
U0 Receiver
Buffer
Register
U0 Transmit
Holding
Register
U0 Divisor
Latch LSB
U0 Interrupt
Enable
0
Register
U0 Divisor
Latch MSB
U0 Interrupt
FIFOs Enabled
ID Register
U0 FIFO
Control
Rx Trigger
Register
U0 Line
Set
Control
DLAB
Break
Register
Int. on
Cpt.3
Int. on
Int. on
Int. on
Cpt.1
Cpt.1
Cpt.1
falling
rising
32 bit data
32 bit data
32 bit data
32 bit data
External Match
External Match
Ext.
Control 0
Mtch.3
8 bit data
8 bit data
8 bit data
0
0
0
0
8 bit data
0
0
IIR3
-
-
Even
Stick
Parity
Parity
Parity
Enable
Select
24
LPC2119/2129/2194/2292/2294
LSB
Int. on
Int. on
Int. on
Cpt.3
Cpt.3
Cpt.2
falling
rising
Int. on
Int. on
Int. on
Cpt.0
Cpt.0
Cpt.0
falling
rising
External Match
Control 3
Control 2
Ext.
Ext.
Ext.
Mtch2.
Mtch.1
Mtch.0
En. Rx
Enable
En. Rx
Line
THRE
Data
Status
Int.
Av.Int.
Int.
IIR2
IIR1
IIR0
U0 Tx
U0 Rx
U0
-
FIFO
FIFO
FIFO
Reset
Reset
Enable
Nm. of
Word Length
Stop
Select
Bits
Preliminary User Manual
Reset
Access
Value
R/W
0
RO
0
RO
0
RO
0
RO
0
R/W
0
un-
RO
defined
WO
NA
R/W
0x01
R/W
0
R/W
0
RO
0x01
WO
0
R/W
0
May 03, 2004
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