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21.4.2
Setting Slave address
I
2
C devices have a unique slave address to identify each device.
The I2CS module supports 7-bit address (does not support 10-bit address), and the address of this module must be
set to SADRS[6:0]/I2CS_SADRS register.
21.4.3
Optional Functions
The I2CS module has a clock stretch, asynchronous address detection, and noise filter optional functions selectable
in the application program.
Clock stretch function
After data and ACK are transmitted or received, the slave device may issue a wait request to the master device
until it is ready to transmit/receive by pulling the I
clock stretch function.
The master device enters a standby state until the wait request is canceled (the SCL line goes high). The clock
stretch function in this module is disabled by default. When using the clock stretch function, set CLKSTR_EN/
I2CS_CTL register to 1 before starting data communication. Note that the data setup time (after the SDA1 pin
outputs the MSB of SDATA[7:0]/I2CS_TRNS register until I2CS turns the SCL1 pin pull-down resistor off)
while the I2CS module is operating with the clock stretch function enabled varies depending on the I2CS mod-
ule operating clock (PCLK) frequency.
asynchronous address detection function
The I2CS module operation clock (PCLK) frequency must be set eight-times or higher than the transfer rate
during data transfer. However, the PCLK frequency can be lowered to reduce current consumption if no other
processing is required during standby for data transfer. The asynchronous address detection function is provided
to detect the I
2
C slave address sent from the master in this status.
The asynchronous address detection function in this module is disabled by default. When using the asynchro-
nous address detection function, set ASDET_EN/I2CS_CTL register to 1.
If the slave address sent from the master has matched with one that has been set in this I2CS module when the
asynchronous address detection function has been enabled, the I2CS module generates a bus status interrupt
and returns NAK to the I
Set the PCLK frequency to eight-times or higher than the transfer rate and reset ASDET_EN to 0 in the inter-
rupt handler routine. Data transfer will be able to resume normally after the master retries transmission. After
the master generates a stop condition to put the I
function can be enabled again to lower the operating speed.
notes: • When the asynchronous address detection function is enabled, the I
without passing through the noise filter. Therefore, the slave address may not be detected in a
high-noise environment.
• When the asynchronous address detection function is enabled, data transfer cannot be per-
formed even if the PCLK frequency is eight-times or higher than the transfer rate. Be sure to
disable the asynchronous address detection function during normal operation.
noise filter
The I2CS module includes a function to remove noise from the SDA1 and SCL1 input signals. This function is
enabled by setting NF_EN/I2CS_CTL register to 1.
21.5
Data Transfer Control
Make the following settings before starting data transfers.
(1) Initialize the I2CS module. See Section 21.4.
(2) Set the interrupt conditions to use I2CS interrupt. See Section 21.6.
note: Make sure that the I2CS module is disabled (I2CSEN/I2CS_CTL register = 0) before setting the
conditions above.
S1C17624/604/622/602/621 TeChniCal Manual
2
C master to request for resending the slave address.
Seiko epson Corporation
2
C bus SCL line down to low. The I2CS module supports this
2
C bus into free status, the asynchronous address detection
2
21 i
C SlaVe (i2CS)
2
C bus signals are input
21-3
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