Table of Contents
Advertisement
Default
name
i/O
status
P51
I/O I (Pull-up) I/O port pin
SOUT1 O
TOUTA5 O
CAPA5
I
P52
I/O I (Pull-up) I/O port pin
SIN1
I
TOUTB5 O
CAPB5
I
P53
I/O I (Pull-up) I/O port pin
#BFR
I
P54
I/O I (Pull-up) I/O port pin
LFRO O
P55
I/O I (Pull-up) I/O port pin
TOUTA6 O
CAPA6
I
P56
I/O I (Pull-up) I/O port pin
TOUTB6 O
CAPB6
I
SeG0–35
O
O (L)
SeG36–39
O
O (L)
COM7–4 O
SeG40–51
O
O (L)
SeG52–55
O
O (L)
COM7–4 O
COM0–3
O
O (L)
#ReSeT
I
I (Pull-up) Initial reset input pin
TeST
I
I
#TeST
I
I
note: DCLK pin initial status
The DCLK pin of the S1C17624/604/622 goes high after the #RESET pin is set to 1 (after reset
status is canceled). The DCLK pin must be set to low with the pull-down resistor in the IC while
the #RESET pin is set to 0 (reset status), therefore do not connect any circuit such as a pull-up
resistor that may set the pin to high.
The S1C17602/621 DCLK pin goes high while the #RESET pin is set to 0 (reset status).
S1C17624/604/622/602/621 TeChniCal Manual
Function
UART Ch.1 data output pin
T16A2 Ch.0 TOUT A signal output pin
T16A2 Ch.0 capture A trigger signal input pin
UART Ch.1 data input pin
T16A2 Ch.0 TOUT B signal output pin
T16A2 Ch.0 capture B trigger signal input pin
I
C slave bus free request input pin
2
LCD frame signal output pin
T16A2 Ch.1 TOUT A signal output pin
T16A2 Ch.1 capture A trigger signal input pin
T16A2 Ch.1 TOUT B signal output pin
T16A2 Ch.1 capture B trigger signal input pin
LCD segment output pins
LCD segment output pins
LCD common output pins
LCD segment output pins
LCD segment output pins
LCD common output pins
LCD common output pins
Test input pin (Connect to V
SS
Test input pin (Connect to V
DD
Seiko epson Corporation
for normal operation.)
for normal operation.)
1 OVeRVieW
available ( )/unavailable (–)
17624 17604 17622 17602 17621
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
1-19
Advertisement
Table of Contents
