Epson S1C17M12 Manuals

Manuals and User Guides for Epson S1C17M12. We have 1 Epson S1C17M12 manual available for free PDF download: Technical Manual

Epson S1C17M12 Technical Manual (253 pages)

CMOS 16-BIT SINGLE CHIP MICROCONTROLLER

Brand: Epson | Category: Microcontrollers | Size: 7.55 MB

Notational Conventions and Symbols in this Manual
3
Table of Contents
4
Overview
13
Features
13
Block Diagram
15
Pins
16
Pin Configuration Diagram (TQFP12-48PIN)
16
Pad Configuration Diagram (Chip)
18
Pin Descriptions
20
Power Supply, Reset, and Clocks
23
Power Generator (PWG)
23
Overview
23
Pins
23
D1 Regulator Operation Mode
24
System Reset Controller (SRC)
24
Overview
24
Input Pin
25
Reset Sources
25
Initialization Conditions (Reset Groups)
26
Clock Generator (CLG)
26
Overview
26
Input/Output Pins
27
Clock Sources
27
Operations
28
Operating Mode
31
Initial Boot Sequence
31
Transition between Operating Modes
32
Interrupts
33
Control Registers
33
PWG V D1 Regulator Control Register
33
CLG System Clock Control Register
33
CLG Oscillation Control Register
35
CLG OSC3 Control Register
35
CLG Interrupt Flag Register
36
CLG Interrupt Enable Register
37
CLG FOUT Control Register
37
CPU and Debugger
39
Overview
39
CPU Core
40
CPU Registers
40
Instruction Set
40
Reading PSR
40
I/O Area Reserved for the S1C17 Core
40
Debugger
40
Debugging Functions
40
Resource Requirements and Debugging Tools
41
List of Debugger Input/Output Pins
41
External Connection
41
Flash Security Function
42
Control Register
42
MISC PSR Register
42
Debug RAM Base Register
43
Memory and Bus
44
Overview
44
Bus Access Cycle
44
Flash Memory
45
Flash Memory Pin
45
Flash Bus Access Cycle Setting
45
Flash Programming
46
Ram
46
Peripheral Circuit Control Registers
46
System-Protect Function
49
Control Registers
50
MISC System Protect Register
50
MISC IRAM Size Register
50
FLASHC Flash Read Cycle Register
50
Interrupt Controller (ITC)
51
Overview
51
Vector Table
51
Vector Table Base Address (TTBR)
52
Initialization
53
Maskable Interrupt Control and Operations
53
Peripheral Circuit Interrupt Control
53
ITC Interrupt Request Processing
53
Conditions to Accept Interrupt Requests by the CPU
54
Nmi
54
Software Interrupts
54
Interrupt Processing by the CPU
54
Control Registers
55
MISC Vector Table Address Low Register
55
MISC Vector Table Address High Register
55
ITC Interrupt Level Setup Register X
55
O Ports (PPORT)
57
Overview
57
I/O Cell Structure and Functions
58
Schmitt Input
58
Over Voltage Tolerant Fail-Safe Type I/O Cell
58
Pull-Up/Pull-Down
58
CMOS Output and High Impedance State
59
High-/Low-Level High-Current Drive Outputs
59
Clock Settings
59
PPORT Operating Clock
59
Clock Supply in SLEEP Mode
59
Clock Supply in DEBUG Mode
59
Operations
60
Initialization
60
Port Input/Output Control
61
Interrupts
62
Px Port Data Register
63
Px Port Enable Register
63
Px Port Pull-Up/Down Control Register
63
Px Port Interrupt Flag Register
64
Px Port Interrupt Control Register
64
Px Port Chattering Filter Enable Register
64
Px Port Mode Select Register
65
Px Port Function Select Register
65
P Port Clock Control Register
65
P Port Interrupt Flag Group Register
67
Control Register and Port Function Configuration of this IC
68
P0 Port Group
68
P1 Port Group
69
P2 Port Group
70
P4 Port Group
71
P5 Port Group
72
Pd Port Group
73
Common Registers between Port Groups
74
Universal Port Multiplexer (UPMUX)
75
Overview
75
Peripheral Circuit I/O Function Assignment
75
Control Registers
76
Pxy-Xz Universal Port Multiplexer Setting Register
76
Watchdog Timer (WDT2)
77
Overview
77
Clock Settings
77
WDT2 Operating Clock
77
Clock Supply in DEBUG Mode
77
Operations
78
WDT2 Control
78
Operations in HALT and SLEEP Modes
79
Control Registers
79
WDT2 Clock Control Register
79
WDT2 Control Register
80
WDT2 Counter Compare Match Register
80
Supply Voltage Detector (SVD3)
82
Overview
82
Input Pins and External Connection
83
Input Pins
83
External Connection
83
Clock Settings
83
SVD3 Operating Clock
83
Clock Supply in SLEEP Mode
83
Clock Supply in DEBUG Mode
84
Operations
84
SVD3 Control
84
SVD3 Operations
85
SVD3 Interrupt and Reset
85
SVD3 Interrupt
85
SVD3 Reset
86
Control Registers
86
SVD3 Clock Control Register
86
SVD3 Control Register
87
SVD3 Status and Interrupt Flag Register
88
SVD3 Interrupt Enable Register
89
16-Bit Timers (T16)
90
Overview
90
Input Pin
90
Clock Settings
91
T16 Operating Clock
91
Clock Supply in SLEEP Mode
91
Clock Supply in DEBUG Mode
91
Event Counter Clock
91
Operations
91
Initialization
91
Counter Underflow
92
Operations in Repeat Mode
92
Operations in One-Shot Mode
92
Counter Value Read
93
Interrupt
93
Control Registers
93
T16 Ch.n Clock Control Register
93
T16 Ch.n Control Register
94
T16 Ch.n Reload Data Register
95
T16 Ch.n Counter Data Register
95
T16 Ch.n Interrupt Flag Register
95
T16 Ch.n Interrupt Enable Register
96
Uart (Uart3)
97
Overview
97
Input/Output Pins and External Connections
98
List of Input/Output Pins
98
External Connections
98
Input Pin Pull-Up Function
98
Output Pin Open-Drain Output Function
98
Input/Output Signal Inverting Function
98
Clock Settings
98
UART3 Operating Clock
98
Clock Supply in SLEEP Mode
99
Clock Supply in DEBUG Mode
99
Baud Rate Generator
99
Data Format
99
Operations
100
Initialization
100
Data Transmission
101
Data Reception
102
Irda Interface
103
Carrier Modulation
103
Receive Errors
104
Framing Error
104
Parity Error
104
Overrun Error
105
Interrupts
105
Control Registers
105
UART3 Ch.n Clock Control Register
105
UART3 Ch.n Mode Register
106
UART3 Ch.n Baud-Rate Register
107
UART3 Ch.n Control Register
108
UART3 Ch.n Transmit Data Register
108
UART3 Ch.n Receive Data Register
108
UART3 Ch.n Status and Interrupt Flag Register
109
UART3 Ch.n Interrupt Enable Register
110
UART3 Ch.n Carrier Waveform Register
110
Synchronous Serial Interface (SPIA)
111
Overview
111
Input/Output Pins and External Connections
112
List of Input/Output Pins
112
External Connections
112
Pin Functions in Master Mode and Slave Mode
113
Input Pin Pull-Up/Pull-Down Function
113
Clock Settings
113
SPIA Operating Clock
113
Clock Supply in DEBUG Mode
114
SPI Clock (Spiclkn) Phase and Polarity
114
Data Format
115
Operations
115
Initialization
115
Data Transmission in Master Mode
115
Data Reception in Master Mode
117
Terminating Data Transfer in Master Mode
118
Data Transfer in Slave Mode
118
Terminating Data Transfer in Slave Mode
120
Interrupts
120
Control Registers
121
SPIA Ch.n Mode Register
121
SPIA Ch.n Control Register
122
SPIA Ch.n Transmit Data Register
123
SPIA Ch.n Receive Data Register
123
SPIA Ch.n Interrupt Flag Register
123
SPIA Ch.n Interrupt Enable Register
124
C (I2C)
125
Overview
125
Input/Output Pins and External Connections
126
List of Input/Output Pins
126
External Connections
126
Clock Settings
127
I2C Operating Clock
127
Clock Supply in DEBUG Mode
127
Baud Rate Generator
127
Operations
128
Initialization
128
Data Transmission in Master Mode
129
Data Reception in Master Mode
131
10-Bit Addressing in Master Mode
133
Data Transmission in Slave Mode
134
Data Reception in Slave Mode
136
Slave Operations in 10-Bit Address Mode
138
Automatic Bus Clearing Operation
138
Error Detection
139
Interrupts
140
Control Registers
141
I2C Ch.n Clock Control Register
141
I2C Ch.n Mode Register
142
I2C Ch.n Baud-Rate Register
142
I2C Ch.n Own Address Register
142
I2C Ch.n Control Register
143
I2C Ch.n Transmit Data Register
144
I2C Ch.n Receive Data Register
144
I2C Ch.n Status and Interrupt Flag Register
144
I2C Ch.n Interrupt Enable Register
145
16-Bit PWM Timers (T16B)
147
Overview
147
Input/Output Pins
148
Clock Settings
149
T16B Operating Clock
149
Clock Supply in SLEEP Mode
149
Clock Supply in DEBUG Mode
149
Event Counter Clock
149
Operations
150
Initialization
150
Counter Block Operations
151
Comparator/Capture Block Operations
154
TOUT Output Control
162
Interrupt
168
Control Registers
168
T16B Ch.n Clock Control Register
168
T16B Ch.n Counter Control Register
169
T16B Ch.n Max Counter Data Register
170
T16B Ch.n Timer Counter Data Register
170
T16B Ch.n Counter Status Register
171
T16B Ch.n Interrupt Flag Register
172
T16B Ch.n Interrupt Enable Register
173
T16B Ch.n Comparator/Capture M Control Register
174
T16B Ch.n Compare/Capture M Data Register
176
IR Remote Controller (REMC2)
177
Overview
177
Input/Output Pins and External Connections
177
Output Pin
177
External Connections
178
Clock Settings
178
REMC2 Operating Clock
178
Clock Supply in SLEEP Mode
178
Clock Supply in DEBUG Mode
178
Operations
178
Initialization
178
Data Transmission Procedures
179
REMO Output Waveform
179
Continuous Data Transmission and Compare Buffers
181
Interrupts
182
Application Example: Driving el Lamp
183
Control Registers
183
REMC2 Clock Control Register
183
REMC2 Data Bit Counter Control Register
184
REMC2 Data Bit Counter Register
185
REMC2 Data Bit Active Pulse Length Register
186
REMC2 Data Bit Length Register
186
REMC2 Status and Interrupt Flag Register
186
REMC2 Interrupt Enable Register
187
REMC2 Carrier Waveform Register
187
REMC2 Carrier Modulation Control Register
188
Seven-Segment LED Controller (LEDC)
189
Overview
189
Output Pins and External Connections
190
List of Output Pins
190
Clock Settings
190
LEDC Operating Clock
190
Clock Supply in SLEEP Mode
190
Clock Supply in DEBUG Mode
191
LED Lighting Cycle
191
Operations
191
Initialization
191
Display On/Off
192
Common Mode
192
Number of Display Digits
192
Brightness Adjustment
192
Display Data Registers
193
Drive Waveform
193
Interrupt
194
Control Registers
194
LEDC Clock Control Register
194
LEDC Control Register
195
LEDC Lighting Period Setting Register
196
LEDC Interrupt Flag Register
196
LEDC Interrupt Enable Register
196
LEDC Comxy Data Registers
196
12-Bit A/D Converter (ADC12A)
197
Overview
197
Input Pins and External Connections
198
List of Input Pins
198
External Connections
198
Clock Settings
198
ADC12A Operating Clock
198
Sampling Time
198
Operations
199
Initialization
199
Conversion Start Trigger Source
199
Conversion Mode and Analog Input Pin Settings
200
A/D Conversion Operations and Control Procedures
200
Interrupts
202
Control Registers
202
ADC12A Ch.n Control Register
202
ADC12A Ch.n Trigger/Analog Input Select Register
203
ADC12A Ch.n Configuration Register
204
ADC12A Ch.n Interrupt Flag Register
205
ADC12A Ch.n Interrupt Enable Register
206
ADC12A Ch.n Result Register M
206
Multiplier/Divider (COPRO2)
207
Overview
207
Operation Mode and Output Mode
207
Multiplication
208
Division
209
Mac
211
Reading Operation Results
213
Electrical Characteristics
214
Absolute Maximum Ratings
214
Recommended Operating Conditions
214
Current Consumption
215
System Reset Controller (SRC) Characteristics
216
Clock Generator (CLG) Characteristics
217
Flash Memory Characteristics
218
Input/Output Port (PPORT) Characteristics
218
Supply Voltage Detector (SVD3) Characteristics
220
UART (UART3) Characteristics
222
Synchronous Serial Interface (SPIA) Characteristics
222
I 2 C (I2C) Characteristics
223
12-Bit A/D Converter (ADC12A) Characteristics
224
Basic External Connection Diagram
225
Package
226
Appendix A List of Peripheral Circuit Control Registers
227
Power Generator (PWG)
227
Appendix B Power Saving
245
Operating Status Configuration Examples for Power Saving
245
Other Power Saving Methods
246
Appendix C Mounting Precautions
247
Appendix D Measures against Noise
249
Appendix E Initialization Routine
250
Revision History
252

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Epson S1C17M12 Technical Manual (253 pages)

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