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D10
aDiBS: aDC10 Status Bit
Indicates the A/D converter status.
1 (R):
Being converted
0 (R):
Conversion completed/standby (default)
ADIBS is set to 1 at the input trigger signal edge (at the beginning of sampling) and is reset to 0 upon
completion of conversion (when ADCTL is set to 0).
D9
aDOWe: Overwrite error Flag Bit
Indicates that the converted results in ADD[15:0]/ADC10_ADD register have been overwritten before
reading.
1 (R):
Overwrite error (cause of interrupt has occurred)
0 (R):
Normal (cause of interrupt has not occurred) (default)
1 (W):
Flag is reset
0 (W):
Ignored
When a single channel or multiple channels are being converted continuously, ADD[15:0] is overwritten
and ADOWE is set to 1 if the A/D conversion currently underway is completed while ADCF is set to 1
(before reading the previous conversion results). After the conversion results are read from ADD[15:0],
ADOWE should be read to check whether the read data is valid or not.
ADOWE is a cause of ADC10 interrupt. When ADOWE is set to 1, a conversion data overwrite error
interrupt request is output to the ITC if ADOIE has been set to 1 (interrupt enabled). An interrupt is
generated if the ITC and S1C17 Core interrupt conditions are satisfied.
ADOWE is reset by writing 1.
D8
aDCF: Conversion Completion Flag Bit
Indicates that A/D conversion has been completed.
1 (R):
Conversion completed (cause of interrupt has occurred)
0 (R):
Being converted/standby (cause of interrupt has not occurred) (default)
ADCF is set to 1 when A/D conversion is completed, and the converted data is loaded into ADD[15:0]/
ADC10_ADD register.
ADCF is a cause of ADC10 interrupt. When ADCF is set to 1, a conversion completion interrupt re-
quest is output to the ITC if ADCIE has been set to 1 (interrupt enabled). An interrupt is generated if the
ITC and S1C17 Core interrupt conditions are satisfied. ADCF is reset to 0 by reading ADD[15:0]. An
overwrite error occurs if the next A/D conversion is completed while ADCF is set (see ADOWE above),
ADCF must be reset by reading ADD[15:0] before an overwrite occurs. When an overwrite error oc-
curs, ADCF is also set due to completion of conversion.
D[7:6]
Reserved
D5
aDOie: Overwrite error interrupt enable Bit
Enables or disables interrupts caused by occurrences of conversion data overwrite errors.
1 (R/W): Interrupt enabled
0 (R/W): Interrupt disabled (default)
Setting ADOIE to 1 enables conversion data overwrite error interrupt requests to the ITC; setting to 0
disables interrupts.
D4
aDCie: Conversion Completion interrupt enable Bit
Enables or disables interrupts caused by completion of conversion.
1 (R/W): Interrupt enabled
0 (R/W): Interrupt disabled (default)
Setting ADCIE to 1 enables conversion completion interrupt requests to the ITC; setting to 0 disables
interrupts.
D[3:2]
Reserved
S1C17624/604/622/602/621 TeChniCal Manual
Seiko epson Corporation
24 a/D COnVeRTeR (aDC10)
24-11
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