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aPPenDiX a liST OF i/O ReGiSTeRS
0x5340–0x5346
Register name address
Bit
ReMC
0x5340
D15–12 CGClK[3:0] Carrier generator clock division
Configuration
(16 bits)
Register
(ReMC_CFG)
D11–8 lCClK[3:0] Length counter clock division ratio
D7–2 –
D1
D0
ReMC Carrier
0x5342
D15–14 –
length Setup
(16 bits)
D13–8 ReMCl[5:0] Carrier L length setup
Register
D7–6 –
(ReMC_CaR)
D5–0 ReMCh[5:0] Carrier H length setup
ReMC length
0x5344
D15–8 ReMlen[7:0] Transmit/receive data length count
Counter Register
(16 bits)
D7–1 –
(ReMC_lCnT)
D0
ReMC interrupt
0x5346
D15–11 –
Control Register
(16 bits)
D10
(ReMC_inT)
D9
D8
D7–3 –
D2
D1
D0
0x5380–0x5386
Register name address
Bit
a/D Conversion
0x5380
D15–0 aDD[15:0]
Result Register
(16 bits)
(aDC10_aDD)
a/D Trigger/
0x5382
D15–14 –
Channel Select
(16 bits)
D13–11 aDCe[2:0] End channel select
Register
D10–8 aDCS[2:0] Start channel select
(aDC10_TRG)
D7
D6
D5–4 aDTS[1:0]
D3
D2–0 aDST[2:0]
aP-a-24
name
Function
ratio select
select
reserved
ReMMD
REMC mode select
ReMen
REMC enable
reserved
reserved
(down counter)
reserved
ReMDT
Transmit/receive data
reserved
ReMFiF
Falling edge interrupt flag
ReMRiF
Rising edge interrupt flag
ReMuiF
Underflow interrupt flag
reserved
ReMFie
Falling edge interrupt enable
ReMRie
Rising edge interrupt enable
ReMuie
Underflow interrupt enable
name
Function
A/D converted data
ADD[9:0] are effective when
STMD = 0 (ADD[15:10] = 0)
ADD[15:6] are effective when
STMD = 1 (ADD[5:0] = 0)
reserved
STMD
Conversion result storing mode
aDMS
Conversion mode select
Conversion trigger select
–
reserved
Sampling time setting
Seiko epson Corporation
iR Remote Controller
Setting
init. R/W
CGCLK[3:0]
0x0 R/W Source clock = PCLK
Division ratio
LCCLK[3:0]
0xf
reserved
0xe
1/16384
0xd
1/8192
0xc
1/4096
0xb
1/2048
0xa
1/1024
0x9
1/512
0x8
1/256
0x0 R/W
0x7
1/128
0x6
1/64
0x5
1/32
0x4
1/16
0x3
1/8
0x2
1/4
0x1
1/2
0x0
1/1
–
1 Receive
0 Transmit
1 Enable
0 Disable
–
0x0 to 0x3f
0x0 R/W
–
0x0 to 0x3f
0x0 R/W
0x0 to 0xff
0x0 R/W
–
1 1 (H)
0 0 (L)
–
1 Cause of
0 Cause of
interrupt
interrupt not
occurred
occurred
–
1 Enable
0 Disable
1 Enable
0 Disable
1 Enable
0 Disable
Setting
init. R/W
0x0 to 0x3ff
0x0
–
0x0 to 0x7
0x0 R/W
0x0 to 0x7
0x0 R/W
1 ADD[15:6]
0 ADD[9:0]
1 Continuous 0 Single
ADTS[1:0]
Trigger
0x0 R/W
0x3
#ADTRG pin
0x2
reserved
0x1
T16 Ch.0
0x0
Software
–
ADST[2:0]
Sampling time 0x7 R/W
0x7
9 cycles
0x6
8 cycles
0x5
7 cycles
0x4
6 cycles
0x3
5 cycles
0x2
4 cycles
0x1
3 cycles
0x0
2 cycles
S1C17624/604/622/602/621 TeChniCal Manual
Remarks
–
–
0 when being read.
0
R/W
0
R/W
–
–
0 when being read.
–
–
0 when being read.
–
–
0 when being read.
0
R/W
–
–
0 when being read.
0
R/W Reset by writing 1.
0
R/W
0
R/W
–
–
0 when being read.
0
R/W
0
R/W
0
R/W
a/D Converter
Remarks
R
–
–
0 when being read.
0
R/W
0
R/W
–
–
0 when being read.
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