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6 inTeRRuPT COnTROlleR (iTC)
6.4
nMi
In the S1C17624/604/622/602/621, the watchdog timer can generate a non-maskable interrupt (NMI). The vector
number for NMI is 2, with the vector address set to the vector table's starting address + 8 bytes.
This interrupt takes precedence over other interrupts and is unconditionally accepted by the S1C17 Core.
For detailed information on generating NMI, see the "Watchdog Timer (WDT)" chapter.
6.5
Software interrupts
The S1C17 Core provides the "int imm5" and "intl imm5,imm3" instructions allowing the software to gener-
ate any interrupts. The operand imm5 specifies a vector number (0–31) in the vector table. In addition to this, the
intl instruction has the operand imm3 to specify the interrupt level (0–7) to be set to the IL field in the PSR.
The processor performs the same interrupt processing as that of the hardware interrupt.
6.6
halT and SleeP Mode Cancellation
HALT and SLEEP modes are cleared by the following signals, which start the CPU.
• Interrupt request signal sent to the CPU from the ITC
• NMI signal output by the watchdog timer
• Debug interrupt signal
• Reset signal
notes: • If the CPU is able to receive interrupts when HALT or SLEEP mode has been cleared by an
interrupt request for the CPU from the ITC, processing branches to the interrupt handler rou-
tine immediately after cancellation. In all other cases, the program is executed following the
halt or slp instruction.
• HALT or SLEEP mode clearing due to interrupt requests cannot be masked (prohibited) using
ITC interrupt level settings.
For more information, see "Power Saving by Clock Control" in the appendix chapter. For the oscillator circuit and
system clock statuses after HALT or SLEEP mode is canceled, see the "Clock Generator (CLG)" chapter.
6.7
Control Register Details
address
Register name
0x4306
ITC_LV0
Interrupt Level Setup Register 0
0x4308
ITC_LV1
Interrupt Level Setup Register 1
0x430a
ITC_LV2
Interrupt Level Setup Register 2
0x430c
ITC_LV3
Interrupt Level Setup Register 3
0x430e
ITC_LV4
Interrupt Level Setup Register 4
0x4310
ITC_LV5
Interrupt Level Setup Register 5
0x4312
ITC_LV6
Interrupt Level Setup Register 6
0x4314
ITC_LV7
Interrupt Level Setup Register 7
0x4316
ITC_LV8
Interrupt Level Setup Register 8
0x4318
ITC_LV9
Interrupt Level Setup Register 9
The ITC registers are described in detail below. These are 16-bit registers.
notes: • After the S1C17622 power is turned on, write the specified values to the addresses shown be-
low before executing the interrupt enable (ei) instruction.
1. Address 0x5140 = 0x01 (in 8-bit access)
2. Address 0x5141 = 0x06 (in 8-bit access)
• After the S1C17624/604 power is turned on, clear the RTC interrupt flag and then disable RTC
interrupts as shown below before executing the interrupt enable (ei) instruction.
1. RTCIRQ/RTC_INTSTAT register = 1 (clear RTC interrupt flag)
2. RTCIEN/RTC_INTMODE register = 0 (disable RTC interrupt)
6-6
Table 6.
7.1 List of ITC Registers
Sets the P0 and P1 interrupt levels.
Sets the SWT and CT/RTC interrupt levels.
Sets the T8OSC1 and SVD interrupt levels.
Sets the LCD/T16A2 Ch.0 and T16E Ch.0 interrupt levels.
Sets the T8F Ch.0&1 and T16 Ch.0 interrupt levels.
Sets the T16 Ch.1 and T16 Ch.2 interrupt levels.
Sets the UART Ch.0 and I2CS/UART Ch.1 interrupt levels.
Sets the SPI Ch.0 and I2CM interrupt levels.
Sets the REMC and T16A2 Ch.1 interrupt levels.
Sets the ADC10 and RFC interrupt levels.
Seiko epson Corporation
Function
S1C17624/604/622/602/621 TeChniCal Manual
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