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Instruc- Mnemonic
tion
Group
Increase/ INC
Decrease
Rota-
tion
BCD
Adjust
Bit
Manipu-
lation
www.DataSheet4U.com
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
Operands
r
saddr
DEC
r
saddr
INCW
rp
DECW
rp
ROR
A, 1
ROL
A, 1
RORC
A, 1
ROLC
A, 1
ROR4
[HL]
ROL4
[HL]
ADJBA
ADJBS
MOV1
CY, saddr.bit
CY, sfr.bit
CY, A.bit
CY, PSW.bit
CY, [HL].bit
saddr.bit, CY
sfr.bit, CY
A.bit, CY
PSW.bit, CY
[HL].bit, CY
register (PCC).
2. Clock indicates when a program is in the internal ROM area.
3. n is the number of waits when the external memory expansion area is read.
4. m is the number of waits when the external memory expansion area is written.
CHAPTER 23 INSTRUCTION SET
Byte
Clock
Note 1
Note 2
1
4
—
2
8
12
1
4
—
2
8
12
1
8
—
1
8
—
1
4
—
1
4
—
1
4
—
1
4
—
2
20
24 + 2n + 2m
2
20
24 + 2n + 2m
2
8
—
2
8
—
3
12
14
3
—
14
2
8
—
3
—
14
2
12
14 + 2n
3
12
16
3
—
16
2
8
—
3
—
16
2
12
16 + 2n + 2m
Operation
r ← r+1
(saddr) ← (saddr)+1
r ← r–1
(saddr) ← (saddr)–1
rp ← rp+1
rp ← rp–1
← A
← A
) × 1
(CY, A
, A
7
0
m–1
m
← A
← A
) × 1
(CY, A
, A
0
7
m+1
m
(CY ← A
← CY, A
← A
) × 1
, A
0
7
m–1
m
(CY ← A
← CY, A
← A
) × 1
, A
7
0
m+1
m
← (HL)
← A
A
, (HL)
,
3–0
3–0
7–4
3–0
← (HL)
(HL)
3–0
7–4
← (HL)
← A
A
, (HL)
,
3–0
7–4
3–0
3–0
← (HL)
(HL)
7–4
3–0
Decimal Adjust Accumulator after
Addition
Decimal Adjust Accumulator after
Subtract
CY ← (saddr.bit)
CY ← sfr.bit
CY ← A.bit
CY ← PSW.bit
CY ← (HL).bit
(saddr.bit) ← CY
sfr.bit ← CY
A.bit ← CY
PSW.bit ← CY
(HL).bit ← CY
) selected by processor clock control
CPU
Flag
Z
AC CY
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
511
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