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Symbol
CSIM0 CSIE0
R/W
CSIM01 CSIM00 Serial Interface Channel 0 Clock Selection
R/W
CSIM CSIM CSIM PM25 P25 PM26 P26 PM27 P27
R/W
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R
R/W
CSIE0
Notes
Remark
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries)
<7>
<6>
<5>
4
COI
WUP CSIM04 CSIM03 CSIM02 CSIM01 CSIM00
×
0
Input clock to SCK0 pin from off-chip
1
0
8-bit timer register 2 (TM2) output
1
1
Clock specified with bits 0 to 3 of timer clock selection register 3 (TCL3)
04
03
02
×
0
3-wire serial I/O mode (Refer to 16.4.2 3-wire serial I/O mode operation)
Note 2 Note 2
×
×
1
0
0
0
0
Note 2 Note 2
×
×
1
0
0
1
1
2-wire serial I/O mode (Refer to 16.4.4 2-wire serial I/O mode operation)
or I
2
C bus mode (Refer to 16.4.5 I
WUP
Wake-up Function Control
0
Interrupt request signal generation with each serial transfer in any mode
1
Interrupt request signal generation when the address received after bus release (when CMDD = RELD = 1)
matches the slave address register (SVA) data when SBI mode is used
COI
Slave Address Comparison Result Flag
0
Slave address register (SVA) not equal to serial I/O shift register 0 (SIO0) data
1
Slave address register (SVA) equal to serial I/O shift register 0 (SIO0) data
Serial Interface Channel 0 Operation Control
0
Operation stopped
1
Operation enable
1. Bit 6 (COI) is a Read-Only bit.
2. Can be used freely as port function.
3. When the wake-up function is used, set bit 5 of the interrupt timing specification register (SINT) to 0.
Do not write data to serial I/O shift register 0 (SIO0) during WUP = 1.
4. When CSIE0 = 0, COI becomes 0.
×
: don't care
PM××: Port mode register
P×× : Output latch of port
3
2
1
0
Operating
Start Bit
Mode
SBI mode
MSB
0
1
0
1
2
C bus mode operation)
Note 3
Note 4
Address
When Reset
R/W
FF60H
00H
R/W
Note 1
SI0/SB0/SDA0/
SO0/SB0/SDA1/
P25 Pin Function
P26 Pin Function
P25
SB1
(CMOS
(N-ch open-drain (CMOS
input/output)
input/output)
SB0
P26
(N-ch open-drain (CMOS input/
input/output)
output)
SCK0/SCL/P27
Pin Function
SCK0
input/output)
353
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