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Instruc- Mnemonic
tion
Group
8-bit
ADD
Ope-
ration
ADDC
SUB
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Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
3. Except r = A
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
register (PCC).
2. Clock indicates when a program is in the internal ROM area.
3. n is the number of waits when the external memory expansion area is read.
508
CHAPTER 23 INSTRUCTION SET
Operands
Byte
A, #byte
2
8
saddr, #byte
3
12
A, r
Note 3
2
8
r, A
2
8
A, saddr
2
8
A, !addr16
3
16
A, [HL]
1
8
A, [HL + byte]
2
16
A, [HL + B]
2
16
A, [HL + C]
2
16
A, #byte
2
8
saddr, #byte
3
12
Note 3
A, r
2
8
r, A
2
8
A, saddr
2
8
A, !addr16
3
16
A, [HL]
1
8
A, [HL+byte]
2
16
A, [HL+B]
2
16
A, [HL+C]
2
16
A, #byte
2
8
saddr, #byte
3
12
A, r
Note 3
2
8
r, A
2
8
A, saddr
2
8
A, !addr16
3
16
A, [HL]
1
8
A, [HL+byte]
2
16
A, [HL+B]
2
16
A, [HL+C]
2
16
Clock
Note 1
Note 2
A, CY ← A+byte
—
(saddr), CY ← (saddr)+byte
16
A, CY ← A+r
—
r, CY ← r+A
—
A, CY ← A+(saddr)
10
A, CY ← A+(addr16)
18 + 2n
A, CY ← A+(HL)
10 + 2n
A, CY ← A+(HL+byte)
18 + 2n
A, CY ← A+(HL+B)
18 + 2n
A, CY ← A+(HL+C)
18 + 2n
A, CY ← A+byte+CY
—
(saddr), CY ← (saddr)+byte+CY
16
A, CY ← A+r+CY
—
r, CY ← r+A+CY
—
A, CY ← A+(saddr)+CY
10
A, CY ← A+(addr16)+CY
18 + 2n
A, CY ← A+(HL)+CY
10 + 2n
A, CY ← A+(HL+byte)+CY
18 + 2n
A, CY ← A+(HL+B)+CY
18 + 2n
A, CY ← A+(HL+C)+CY
18 + 2n
A, CY ← A–byte
—
(saddr), CY ← (saddr)–byte
16
A, CY ← A–r
—
r, CY ← r–A
—
A, CY ← A–(saddr)
10
A, CY ← A–(addr16)
18 + 2n
A, CY ← A–(HL)
10 + 2n
A, CY ← A–(HL+byte)
18 + 2n
A, CY ← A–(HL+B)
18 + 2n
A, CY ← A–(HL+C)
18 + 2n
CPU
Operation
Z
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
) selected by processor clock control
Flag
AC CY
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
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