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Names of test input flag and test mask flag corresponding to test input signal name are shown in Table 18-6.
(1) Interrupt request flag register 0H (IF0H)
This register displays the watch timer overflow detection/non-detection.
IF0H is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets IF0H to 00H.
Symbol
7
IF0H
0
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Caution
Be sure to set bits 4, 6, and 7 to 0.
(2) Interrupt mask flag register 0H (MK0H)
This register sets standby mode clear enable/disable by watch timer.
MK0H is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets MK0H to FFH.
Symbol
7
MK0H
1
Caution
Be sure to set bits 4, 6, and 7 to 1.
470
CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCTION
Table 18-6. Various Flags Corresponding to Test Input Signal
Test Input Signal Name
INTWT
INTPT4
Figure 18-18. Interrupt Request Flag Register 0H Format
6
<5>
4
<3>
0
WTIF
0
ADIF
TMIF2 TMIF1 TMIF0
Figure 18-19. Interrupt Mask Flag Register 0H Format
6
<5>
4
<3>
1
WTMK
1
ADMK TMMK2 TMMK1 TMMK0
Test Input Flag
Test Mask Flag
WTIF
WTMK
KRIF
KRMK
<2>
<1>
<0>
Address
FFE1H
WTIF
0
1
<2>
<1>
<0>
Address
FFE5H
WTMK
0
1
When Reset
R/W
00H
R/W
Watch timer overflow detection flag
Non detection
Detection
When Reset
R/W
FFH
R/W
Standby mode control by watch timer
Standby mode clear enabled
Standby mode clear disabled
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