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(d) Clear upon RESET input
Maskable interrupt request
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Non-maskable interrupt request
Test input
RESET input
Remark ×: don't care
The HALT mode is cleared when the RESET signal inputs.
As is the case with normal reset operation, a program is executed after branch to the reset vector address.
Figure 20-3. HALT Mode Clear upon RESET Input
HALT
Instruction
RESET
Signal
Operating
Mode
Clock
Remarks 1. f
: Main system clock oscillation frequency
X
2. Values in parentheses apply to operation with f
Table 20-2. Operation after HALT Mode Clear
Clear Source
MK××
0
0
0
0
0
1
—
0
1
—
CHAPTER 20 STANDBY FUNCTION
Reset
HALT Mode
Period
Oscillation
Oscillation
Stop
PR××
IE
ISP
×
0
0
×
0
1
1
0
1
×
1
0
1
1
1
×
×
×
×
×
—
×
×
—
×
×
—
×
×
—
Wait
(2
18
/f
: 26.2 ms)
X
Oscillation
Operating
Stabilization
Mode
Wait Status
Oscillation
= 10.0 MHz
X
Operation
Next address instruction execution
Interrupt service execution
Next address instruction execution
Interrupt service execution
HALT mode hold
Interrupt service execution
Next address instruction execution
HALT mode hold
Reset processing
487
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