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If a micro DMA request is set for more than one channel at the same time, the
priority is not based on the interrupt priority level but on the channel number. The
smaller channel number has the higher priority (Channel 0 (High) > Channel 3 (Low)).
While the register for setting the transfer source/transfer destination addresses is a
32-bit control register, this register can only effectively output 24-bit addresses.
Accordingly, micro DMA can access 16 Mbytes (The upper 8 bits of the 32 bits are not
valid).
Three micro DMA transfer modes are supported: 1-byte transfer, 2-byte (One word)
transfer, and 4-byte transfer. After a transfer in any mode, the transfer
source/destination addresses are increased, decreased, or remain unchanged.
This simplifies the transfer of data from I/O to memory, from memory to I/O, and
from I/O to I/O. For details of the transfer modes, see 3.4.2 (4) "Detailed description of
the transfer mode register". As the transfer counter is a 16-bit counter, micro DMA
processing can be set for up to 65536 times per interrupt source. (The micro DMA
processing count is maximized when the transfer counter initial value is set to
0000H.)
Micro DMA processing can be started by the 24 interrupts shown in the micro DMA
start vectors of Table 3.4.1 and by the micro DMA soft start, making a total of 25
interrupts.
Figure 3.4.2 shows the word transfer micro DMA cycle in transfer destination
address INC mode (except for counter mode, the same as for other modes).
(The conditions for this cycle are based on an external 16-bit bus, 0 waits, transfer
source/transfer destination addresses both even-numberd values.)
1 state
DM1
X1
A0 to A23
RD
WR / HWR
D0 to D15
States 1 to 3: Instruction fetch cycle (gets next address code).
If 3 bytes and more instruction codes are inserted in the instruction queue buffer, this cycle
becomes a dummy cycle.
States 4 to 5: Micro DMA read cycle
State 6:
Dummy cycle (The address bus remains unchanged from state 5)
States 7 to 8: Micro DMA write cycle
Note 1: If the source address area is an 8-bit bus, it is increased by two states.
If the source address area is a 16-bit bus and the address starts from an odd number, it is increased by
two states.
Note 2: If the destination address area is an 8-bit bus, it is increased by two states.
If the destination address area is a 16-bit bus and the address starts from an odd number, it is increased
by two states.
(Note 1)
DM2
DM3
DM4
DM5
Transfer source address
Input
Figure 3.4.2 Timing for Micro DMA Cycle
91C824-42
(Note 2)
DM6
DM7
DM8
Transfer destination
address
Output
TMP91C824
2008-02-20
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