Table of Contents
Advertisement
fail detection and also to the Reset-Input of the CC (Pin30)
via [7802],whichis necessary to generate a reset only
during power-up. In case of power fail pin 30 of the CC
must be kept high (3V3).
The internal memory of the CC is too small for all
necessary demands. Therefore an external Flash-ROM
[7805] with 1MByte in size and a RAM [7803] with
128kByte are necessary. Both parts are connected to the
P via a parallel address-/data-bus. The lower eight bus-
lines (AD0 to AD7) are multiplexed by [7801] and the
"ALE"-signal of the CC.
For updating of the software the external Flash-ROM can
be reprogrammed by the P. During this process [7807] is
switched on by the "WE"-signal.
When no mains is connected, the CC is supplied via Gold-
Cap [2816] during the power backup period. The diode
[6802] prevents unwanted current consumption of other
components.
The internal ROM of the P holds the program code for the
Real-Time-Clock. Only the microprocessor is supplied by
the backup cell, not the external memories and the P
operates in a low frequency mode with the clock crystal
[1805] only (32.768 kHz). To adjust the clock the
frequency can be measured at pin 87 of the P in a special
test-mode.
2.3 Control-Interfaces
The CC is communicating with the digital board via a serial
connection, which operates at a speed of 19,4 kbit/s
("D_DATA"-, "A_DATA", "D_RDY"- and "A_RDY"-signal
on [1986]). By generating a high level on pin 16 of the CC
the digital PCB can be reset (inverter [7817] in between).
Most of the other parts are controlled by the P via I2C-bus
("SDA"- and "SCL"-signal). The FETs [7821] and [7822]
are used for adaptation of the 3V3-level on CC-side to the
components supplied with 5V.
The CC can also reset the display-board-P by pulling pin
39 to high.
The transistor [7819] acts as a level shifter for the "INT"-
signal.
In the European sets a bi-directional interface is
established between the recording unit and the TV device
at pin 10 of the Scart ("P50"-line/Easy Link). The
processing is done via pin 14 (output) and pin 38 (input) of
the CC and the circuit around [7813], [7814] and [7815].
2.4 EEPROM
The EEPROM M24C16 [7808] is an electrical erasable
and programmable, non-volatile memory. The EEPROM
stores data specific to the device, such as the AFC-
reference value of the Europe IF-part, the clock-
correction-factor, etc. It is accessed by the P via the I2C-
bus.
2.5 Sync Separator
To detect whether a video signal is available or not a
separate IC [7825] is used to extract the sync information
out of the video signal that is also routed to the digital
board for recording.
While on the input a low-pass-filter ([2823] and
[3869])limits the bandwidth an additional filter (circuit
around [7818]) on the output avoids distortions.
Afterwards the sync-signal is routed to pin11 of the CC.
2.6 Fan Control
To avoid unwanted temperatures inside the set (especially
the Laser on the OPU of the drive is very sensitive) a fan is
located on top of the DVDR mechanism. The speed
control is dependent on the ambient temp. A NTC resistor
[3134] located on thedisplay board measures the
temperature. An operational amplifier [7902-B] generates
a proper voltage, which is then fed to the engine
("BE_FAN"-line). Below 28°C ambient temp. the fan-
voltage is approx. 5V and is increased to 10V when the
ambient temperature goes up to approx. 38°C. The
second part of the Op-Amp. [7902-A] prevents damage of
any temperature-sensitive part in case the NTC or the wire
in between is damaged. It acts as a comparator and pulls
the "BE_FAN"-signal to 10V. As the fan has to be stopped
in case the tray of the drive is open this voltage is "killed"
by the CC ("FAN_OFF"-signal).
The double-diode [6901] acts for both Op.-Amp.-circuits.
The circuit is also prepared for a set-fan (circuit around the
Op-Amp. [7902-C] ).
3 Analog board Europe
3.1 General
This PCB consists out of the following parts:
– Power-Supply-Unit
– Frontend (Audio & Video)
– Input-/Output-switching
– Audio ADC- & DAC-processing
– VPS/PDC- and Text-Data slicer
– Analog Follow-Me Circuit
All functional groups are either controlled via I2C-bus or
via separate signal lines by the Central-Controller on the
P-Sub-Board.
This sub board is directly soldered in onto the analog PCB.
During Stand-By mode of the set, several parts are not
supplied (Tuner, MSP, ...). The microprocessor is running
and maintains the clock of the set.
To avoid bus blockades the I2C-bus ("SCLSW" &
"SDASW") to/ from these units is decoupled via transistors
[7419], [7420] from the general bus ("SCL" & "SDA").
DRX-2
99
Advertisement
Table of Contents
