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IC7501: NCP1570D
V
ñ
CC
+
+
8.5 V/7.5 V
ñ
GND
V
FB
+
0.985 V
ñ
COMP
0.525 V
ñ
+
+
ñ
PACKAGE PIN #
SO–8
PIN SYMBOL
1
V CC
2
PWRGD
3
PGDELAY
4
COMP
5
GATE(H)
6
GATE(L)
7
V FB
8
GND
UVLO COMP
ñ
+
+
0.25 V
ñ
Error Amp
ñ
PWM COMP
+
+
ñ
OSC
Art Ramp
80%, 200 kHz
+
0.25 V
ñ
PGDELAY Latch
ñ
S
Q
+
0.89 V/0.69 V
R
Set Dominant
FUNCTION
Power supply input.
Open collector output goes low when V FB is out of regulation. User must externally
limit current into this pin to less than 20 mA.
External capacitor programs PWRGD low–to–high transition delay.
Error amp output. PWM comparator reference input. A capacitor to LGND provides
error amp compensation and Soft Start. Pulling pin < 0.45 locks gate outputs to a zero
percent duty cycle state.
High–side switch FET driver pin. Capable of delivering peak currents of 1.5 A.
Low–side synchronous FET driver pin. Capable of delivering peak currents of 1.5 A.
Error amplifier and PWM comparator input.
Power supply return.
Fault Latch
S
Q
R
Set Dominant
PWM Latch
R
Q
S
Reset Dominant
+
ñ
ñ
+
+
3.3 V
ñ
DRX-2
V
CC
GATE(H)
Non
Overlap
GATE(L)
12 A
PGDELAY
PWRGD
(Unconnected)
125
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