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Table 16-4 and Figure 16-7 show the timing for the external clock output stabilization delay time.
The oscillator and duty correction circuit have the function of regulating the waveform of the
external clock input to the EXTAL pin. When the specified clock signal is input to the EXTAL
pin, internal clock signal output is confirmed after the elapse of the external clock output
stabilization delay time (t
reset signal should be driven low and the reset state maintained during this time.
Table 16-4 External Clock Output Stabilization Delay Time
Conditions: V
= 2.7 V to 5.5 V, AV
CC
Item
External clock output stabilization
delay time
Note: * t
includes a 10 t
DEXT
V
2.7 V
CC
V
STBY
IH
EXTAL
ø
RES
Note: * t
includes a 10 t
DEXT
Figure 16-7 External Clock Output Stabilization Delay Time
). As clock signal output is not confirmed during the t
DEXT
= 2.7 V to 5.5 V, V
CC
Symbol
t
*
DEXT
RES pulse width (t
cyc
t
DEXT
RES pulse width (t
cyc
= AV
SS
Min
Max
500
—
).
RESW
*
).
RESW
period, the
DEXT
= 0 V
SS
Unit
Notes
µs
Figure 16-7
497
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