2. The input capture function cannot be used in PWM mode. If compare match A and compare match B occur simultaneously, the compare match signal is inhibited.

3. Do not set both channels 3 and 4 for synchronous operation when complementary PWM mode is selected.

4. The counter cannot be cleared by input capture A when reset-synchronized PWM mode is selected.

5. In complementary PWM mode, select the same clock source for channels 3 and 4.

6. Use the input capture A function in channel 1.

TMDR

TFCR

Comple-

Reset-

mentary

Synchro-

FDIR PWM

PWM

nized PWM Buffering

—

PWM3 = 1 CMD1 = 0

CMD1 = 0

—

PWM3 = 0 CMD1 = 0

CMD1 = 0

—

CMD1 = 0

—

PWM3 = 0 CMD1 = 0

CMD1 = 0

—

PWM3 = 0 CMD1 = 0

CMD1 = 0

—

Illegal setting:

CMD1 = 1

CMD0 = 0

—

CMD1 = 0

—

Illegal setting:

CMD1 = 1

CMD0 = 0

—

CMD1 = 1

CMD0 = 0

—

CMD1 = 1

CMD0 = 1

—

TOCR

TOER

Output

Level

Master

XTGD Select Enable

—

EA3 ignored IOA2 = 1

Other bits

unrestricted unrestricted

—

EB3 ignored

Other bits

unrestricted

—

BFA3 = 1

—

Other bits

unrestricted

BFB3 = 1

—

Other bits

unrestricted

TIOR3

TCR3

Clear

Clock

IOA

IOB

Select

—

IOA2 = 0

Other bits

unrestricted

IOB2 = 0

Other bits

unrestricted

Other bits

IOB2 = 1

Other bits

unrestricted

CCLR1 = 0

CCLR0 = 1

CCLR1 = 1

CCLR0 = 0

CCLR1 = 1

CCLR0 = 1

—

CCLR1 = 0

CCLR0 = 0

—

CCLR1 = 0

CCLR0 = 1

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Hitachi F-ZTAT H8/3039 Series Hardware Manual page 293

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