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Status Encoding
This section describes symbol information that has been set up by the
analysis probe configuration software. The signal-to-connector tables
in the "Hardware Reference" chapter list all the CPU32 signals probed
and their corresponding analyzer channels.
The table below describes each of the bits of the STAT label. This table
is specifically for a state configuration. The timing configurations have
many of the same signals, and those signals are represented by the
same symbols used for state configurations.
HP E2480A STAT Bit Description
Bit
STAT Label
0
~ShoCy
1
Rd/~Wr
2
~IFtch
3
~PFlsh
4:5
Sizx
6:7
DSAckx
8
~BErr
9
~Freeze
10
~Bkpt
11
~BGAck
12:14
FCx
Solutions for CPU32
Chapter 4: Analyzing the CPU32 with a Logic Analyzer
Description
When this bit is asserted it indicates the
execution of an internal (show) cycle.
Indicates the direction of the transfer.
Indicates the bus cycle is an instruction fetch.
Indicates the instruction pipe has been flushed.
Indicates the number of bytes being written or
capable of being read.
Indicates the port size (in bytes) of the peripheral
being read from/ written to.
Indicates that the bus cycle terminated with an
error.
When asserted, indicates the microcontroller is
in background mode.
Indicates a hardware breakpoint has been
encountered.
When asserted, indicates the microcontroller
does not own the bus.
These bits indicate the area of memory with
which a transfer is taking place.
Logic Analyzer Configuration
95
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