Table of Contents
Advertisement
EP1_SIZE_H_B
(07B1H)
bit Symbol
Read/Write
After reset
EP2_SIZE_H_B
(07B2H)
bit Symbol
Read/Write
After reset
EP3_SIZE_H_B
bit Symbol
(07B3H)
Read/Write
After reset
EP4_SIZE_H_B
bit Symbol
(07B4H)
Read/Write
After reset
bit Symbol
EP5_SIZE_H_B
(07B5H)
Read/Write
After reset
bit Symbol
EP6_SIZE_H_B
Read/Write
(07B6H)
After reset
EP7_SIZE_H_B
bit Symbol
(07B7H)
Read/Write
After reset
Note EP3,4,5,6,7_SIZE_H_B registers are not used at TMP92CZ26A.
DATASIZE[9:7] (H register: Bit2 to bit0)
DATASIZE[6:0] (L register: Bit6 to bit0)
PKT_ACTIVE (L register: Bit7)
1: OUT_ENABLE
0: OUT_DISABLE
7
6
5
7
6
5
7
6
5
7
6
5
7
6
5
7
6
5
7
6
5
92CZ26A-396
4
3
4
3
4
3
4
3
4
3
4
3
4
3
In receiving, data number that 1 packet received
from the host is shown. This is renewed when a data
from the host is received with no error.
When dual-packet mode is selected, this bit show
packet that can be accessed. In this case, the UDC
accesses packets that divide FIFO (Packet A and
Packet B) mutually. When FIFO in UDC is accessed by
CPU, refer to this bit. If receiving endpoint, start
reading from packet that this bit is "1". In single-packet
mode, this bit is no meaning because of the packet-A is
always used.
TMP92CZ26A
2
1
DATASIZE9
DATASIZE8
DATASIZE7
R
R
0
0
2
1
DATASIZE9
DATASIZE8
DATASIZE7
R
R
0
0
2
1
DATASIZE9
DATASIZE8
DATASIZE7
R
R
0
0
2
1
DATASIZE9
DATASIZE8
DATASIZE7
R
R
0
0
2
1
DATASIZE9
DATASIZE8
DATASIZE7
R
R
0
0
2
1
DATASIZE9
DATASIZE8
DATASIZE7
R
R
0
0
2
1
DATASIZE9
DATASIZE8
DATASIZE7
R
R
0
0
0
R
0
0
R
0
0
R
0
0
R
0
0
R
0
0
R
0
0
R
0
Advertisement
Table of Contents
