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lost and SBISR<AL> is set to "1".
When SBISR<AL> is set to "1", SBISR<MST, TRX> are cleared to "00" and the mode is
switched to Slave Receiver Mode. Thus, clock output is stopped in data transfer after
setting <AL>="1".
SBISR<AL> is cleared to "0" when data is written to or read from SBIDBR or when
data is written to SBICR2.
Internal
SCL output
Master
A
D7A
Internal
SDA output
Internal
SCL output
Master
B
Internal
D7B
SDA output
<AL>
<MST>
<TRX>
Accessed to
SBIDBR or SBICR2
Figure 3.15.13 Example of when TMP92CZ26A is a master device B
(11)
Slave address match detection monitor
SBISR<AAS> is set to "1" in Slave Mode, in Address Recognition Mode (i.e. when
I2CAR<ALS> = "0"), when a GENERAL CALL is received, or when a slave address
matches the value set in I2CAR. When I2CAR<ALS> = "1", SBISR<AAS> is set to "1"
after the first word of data has been received. SBISR<AAS> is cleared to "0" when
data is written to or read from the data buffer register SBIDBR.
(12)
GENERAL CALL detection monitor
SBISR<AD0> is set to "1" in Slave Mode, when a GENERAL CALL is received (all
8-bit received data is "0", after a start condition). SBISR<AD0> is cleared to "0" when
a start condition or stop condition is detected on the bus.
(13)
Last received bit monitor
The SDA line value stored at the rising edge of the SCL line is set to the
SBISR<LRB>. In the acknowledge mode, immediately after an INTSBI interrupt
request is generated, an acknowledge signal is read by reading the contents of the
SBISR<LRB>.
1
2
3
4
5
D6A
D5A
D4A
D3A
Stop the clock pulse
1
2
3
4
D6B
Keep Internal SDA output to high-level as losing arbitration
(D7A = D7B, D6A = D6B)
92CZ26A-355
6
7
8
9
D2A
D1A
D0A
TMP92CZ26A
1
2
3
4
D7A' D6A' D5A' D4A'
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