Page 1 32 Bit RISC Microcontroller TX03 Series TMPM3V6/M3V4...
Page 3 TMPM3V6/M3V4 ************************************************************************************************************************* Arm, Cortex and Thumb are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. All rights reserved. *************************************************************************************************************************...
Page 4 Generally, if MCUs operate while the high-impedance pins left open, electrostatic damage or latch-up may occur in the internal LSI due to induced voltage influenced from external noise. Toshiba recommend that each unused pin should be connected to the power supply pins or GND pins via resistors.
Page 5 TMPM3V6/M3V4 Introduction: Notes on the description of SFR (Special Function Register) under this specification An SFR (Special Function Register) is a control register for peripheral circuits (IP). The SFR addresses of IPs are described in the chapter on memory map, and the details of SFR are given in the chapter of each IP.
Page 6 TMPM3V6/M3V4 1.2.2 SAMCR(Control register) bit symbol After reset bit symbol After reset bit symbol MODE After reset bit symbol MODE TDATA After reset Bit Symbol Type Function 31-10 − "0" can be read. MODE[2:0] Operation mode settings 000 : Sample mode 0 001 : Sample mode 1 010 : Sample mode 2 011 : Sample mode 3...
Page 7 Revision History Date Revision Comment 2019-02-06 First Release...
Page 9: Table Of Contents
Table of Contents General precautions on the use of Toshiba MCUs TMPM3V6/M3V4 1.1 Features............................1 1.2 Block Diagram...........................5 1.3 Pin Layout (Top view)......................6 1.3.1 TMPM3V6FWFG.................................6 1.3.2 TMPM3V6FWDFG................................6 1.3.3 TMPM3V4FWUG, TMPM3V4FSUG..........................7 1.3.4 TMPM3V4FWEFG, TMPM3V4FSEFG..........................7 1.4 Pin names and Functions......................8 1.4.1 Pin names and Functions for each peripheral function, control pin and power supply pin................................8...
Page 10 3.3.6 Auxiliary Fault Status register............................28 3.4 Events............................29 3.5 Power Management.........................29 3.6 Exclusive access........................29 4. Memory Map 4.1 Memory Map...........................31 4.2 Bus Matrix..........................34 4.2.1 Structure.....................................35 4.2.1.1 Single chip mode 4.2.1.2 Single boot mode 4.2.2 Connection table................................37 4.2.2.1 Code area / SRAM area 4.2.2.2 Peripheral area / External bus area 4.3 Address lists of peripheral functions..................40...
Page 11 6.6.3 STOP mode..................................65 6.6.4 Low power Consumption Mode Setting...........................66 6.6.5 Operational Status in Each Mode.............................67 6.6.6 Releasing the Low Power Consumption Mode........................68 6.6.7 Warm-up....................................70 6.6.8 Clock Operations in Mode Transition..........................71 6.6.8.1 Transition of operation modes: NORMAL → STOP → NORMAL 6.6.8.2 Transition of operation modes: NORMAL →...
Page 12 8.2.1.2 NFENCR (Noise Filter Enable register) 8.3 Operation Description......................132 8.3.1 Configuration...................................132 8.3.2 Operation..................................132 8.3.3 Noise Filter Usable Operation Mode..........................132 8.3.4 Precautions on Use of STOP Mode..........................132 8.3.5 Minimum Noise Filtering Time............................132 9. Input / Output port 9.1 Registers..........................133 9.1.1 Register list..................................134 9.1.2 Port function and setting list............................135 9.1.2.1...
Page 13 10.5.8 Timer Flip-flop (TBxFF0).............................174 10.5.9 Capture interrupt (INTCAPx0, INTCAPx1).........................174 10.6 Description of Operations for Each Mode................175 10.6.1 16-bit interval Timer Mode............................175 10.6.2 16-bit Event Counter Mode............................175 10.6.3 16-bit PPG (Programmable Pulse Generation) Output Mode..................176 10.6.4 External Trigger PPG (Programmable Square Wave) Output Mode................178 10.6.5 Timer synchronous mode..............................179 10.7 Applications using the Capture Function................180...
Page 14 12.3.7 SCxMOD2 (Mode Control Register 2).........................220 12.3.8 SCxBRCR (Baud Rate Generator Control Register)....................222 12.3.9 SCxBRADD (Baud Rate Generator Control Register 2).....................223 12.3.10 SCxFCNF (FIFO Configuration Register)........................224 12.3.11 SCxRFC (Receive FIFO Configuration Register)......................226 12.3.12 SCxTFC (Transmit FIFO Configuration Register) ....................227 12.3.13 SCxRST (Receive FIFO Status Register)........................228 12.3.14 SCxTST (Transmit FIFO Status Register)........................229...
Page 15 12.14.1 Mode 0 (I/O interface mode)............................255 12.14.1.1 Transmit 12.14.1.2 Receive 12.14.1.3 Transmit and Receive (Full-duplex) 12.14.2 Mode 1 (7-bit UART mode)............................266 12.14.3 Mode 2 (8-bit UART mode)............................266 12.14.4 Mode 3 (9-bit UART mode)............................267 12.14.4.1 Wakeup function 12.14.4.2 Protocol 13. Serial Bus Interface (I2C/SIO) 13.1 Configuration........................270 13.2 Register..........................271 13.2.1...
Page 16 13.8.2 Transfer Modes................................304 13.8.2.1 8-bit transmit mode 13.8.2.2 8-bit receive mode 13.8.2.3 8-bit transmit/receive mode 13.8.2.4 Data retention time of the last bit at the end of transmission 14. Synchronous Serial Port (SSP) 14.1 Overview..........................309 14.2 Block Diagram........................310 14.3 Register..........................311 14.3.1 Register List...................................311 14.3.2...
Page 17 15.4.1.3 Preparation 15.4.1.4 Enabling Reception 15.4.1.5 Stopping Reception 15.4.1.6 Receiving Remote Control Signal without Leader in Waiting Leader 15.4.1.7 A Leader only with "Low" Width 15.4.1.8 Receiving a Remote Control Signal in a Phase Method 16. Analog/Digital Converter (ADC) 16.1 Functions and features......................357 16.2 Block Diagram........................357 16.3 List of Registers........................358 16.4 Register Descriptions......................359...
Page 18 17.3.3.8 RTCYEARR (Year column register (for PAGE0 only)) 17.3.3.9 RTCYEARR (Leap year register (for PAGE1 only)) 17.3.3.10 RTCPAGER(PAGE register(PAGE0/1)) 17.3.3.11 RTCRESTR (Reset register (for PAGE0/1)) 17.4 Operational Description.......................410 17.4.1 Reading clock data................................410 17.4.2 Writing clock data.................................410 17.4.3 Entering the Low Power Consumption Mode......................412 17.5 Alarm function........................413 17.5.1 "Low"...
Page 19 21.3.2 Operation Mode and Status............................435 21.4 Operation when malfunction (runaway) is detected............436 21.4.1 INTWDT interrupt generation............................436 21.4.2 Internal reset generation..............................437 21.5 Control register........................438 21.5.1 Watchdog Timer Mode Register (WDMOD).......................438 21.5.2 Watchdog Timer Control Register(WDCR).........................438 21.5.3 Setting example................................439 21.5.3.1 Disabling control 21.5.3.2 Enabling control 21.5.3.3...
Page 20 22.3.6 Transfer Format at RAM Transfer..........................472 22.3.7 Transfer Format of Flash memory Chip Erase and Protect Bit Erase.................474 22.3.8 Boot Program Whole Flowchart...........................476 22.3.9 Reprogramming Procedure of Flash using reprogramming algorithm in the on-chip BOOT ROM......477 22.3.9.1 Step-1 22.3.9.2 Step-2 22.3.9.3 Step-3 22.3.9.4...
Page 21 25.3 DC Electrical Characteristics (2/3)..................499 25.4 DC Electrical Characteristics (3/3)..................500 25.5 12/10-bit AD Converter Electrical Characteristics.............501 25.6 AC Electrical Characteristics....................502 25.6.1 AC Measurement Condition............................502 25.6.2 Serial Channel (SIO/UART)............................502 25.6.2.1 I/O Interface Mode 25.6.3 Serial Bus Interface (I2C/SIO)............................504 25.6.3.1 I2C Mode 25.6.3.2 Clock-Synchronous 8-bit SIO mode 25.6.4...
Page 23: Tmpm3V6/M3V4
TMPM3V6/M3V4 TMPM3V6/3V4 The TMPM3V6/M3V4 is a 32-bit RISC microprocessor with an Arm® Cortex® -M3 microprocessor core. Features of the TMPM3V6/3V4 are shown as follows: Product name Package (FLASH) TMPM3V6FWFG 128Kbyte 10Kbyte LQFP100 (14x14mm, 0.5mm pitch) TMPM3V6FWDFG 128 Kbyte 10Kbyte QFP100 (14x20mm, 0.65mm pitch) TMPM3V4FWUG 128 Kbyte 10Kbyte...
Page 24 Features TMPM3V6/M3V4 TMPM3V4FSUG, TMPM3V4FSEFG : 8Kbyte 3. Clock controller (CG) ・ Built-in Oscillator (9MHz) ・ External Oscillator (High Frequency 10MHz) ・ External Oscillator (Low Frequency 32.768kHz) ・ Installed 1 unit of Built-in PLL. (4x) ・ Clock gear function: divides high-speed clock into 1/1, 1/2, 1/4, 1/8 or 1/16. 4.
Page 25 TMPM3V6/M3V4 Reset or non-maskable interrupt (NMI) are occurred. 10. Serial channel (SIO/UART) TMPM3V6FWFG, TMPM3V6FWDFG : 3 channel TMPM3V4FWUG, TMPM3V4FWEFG : 2 channel TMPM3V4FSUG, TMPM3V4FSEFG : 2 channel ・ Selectable either UART or synchronous mode (4byte FIFO equipped) 11. Asynchronous serial communication interface (UART): 1 channel ・...
Page 26 Features TMPM3V6/M3V4 21. Maximum operating frequency : 40MHz 22. Operating voltage range ・ 4.5V to 5.5V (all function operation) ・ 3.9V to 4.5V (restrictions of 12-bit ADC) 23. Temperature range ・ −40°C to 85°C (except during Flash writing/erasing and debugging) ・...
Page 27: Block Diagram
TMPM3V6/M3V4 Block Diagram Cortex-M3 FLASH NVIC BOOT Debug AHB Lite (max 40MHz) AHB to IO AHB to APB Bridge Bridge SIO/UART I2C/SIO UART TMRB PORT VLTD IHOSC EHOSC ELOSC Figure 1-1 Block Diagram Page 5 2019-02-06...
Page 28: Pin Layout (Top View)
Pin Layout (Top view) TMPM3V6/M3V4 Pin Layout (Top view) 1.3.1 TMPM3V6FWFG DVSS LQFP100 14x14mm 0.5mm pitch DVDD5 VOUT3 RESET Top View RVDD5 MODE DVSS VOUT15 DVSS DVSS Figure 1-2 Pin Layout (LQFP100 14x14mm TOP VIEW) 1.3.2 TMPM3V6FWDFG DVSS QFP100 14x20mm 0.65mm pitch DVDD5 VOUT3 RESET...
Page 29: Tmpm3V4Fwug, Tmpm3V4Fsug
TMPM3V6/M3V4 1.3.3 TMPM3V4FWUG, TMPM3V4FSUG DVSS LQFP64 10x10mm 0.5mm pitch DVDD5 Top View VOUT3 RESET RVDD5 MODE DVSS VOUT15 DVSS DVSS Figure 1-4 Pin Layout (LQFP64 10x10mm TOP VIEW) 1.3.4 TMPM3V4FWEFG, TMPM3V4FSEFG DVSS QFP64 14x14mm 0.8mm pitch DVDD5 Top View VOUT3 RESET RVDD5 MODE...
Page 30: Pin Names And Functions
Pin names and Functions TMPM3V6/M3V4 Pin names and Functions 1.4.1 Pin names and Functions for each peripheral function, control pin and power supply pin 1.4.1.1 Peripheral functions Table 1-1 The number of pins and Pin names Input Peripheral function Pin name Function Output Clock / Mode control...
Page 31: Control Function
TMPM3V6/M3V4 1.4.1.2 Debug function Table 1-2 Pin name and functions Input Pin name Function Output Input JTAG test mode select input pin Input JTAG serial clock input pin Output JTAG serial data output pin Input JTAG serial data input pin Input JTAG test reset input pin TRST...
Page 32: Power Supply Pins
Pin names and Functions TMPM3V6/M3V4 1.4.1.4 Power supply pins Table 1-4 Pin name and functions Power supply Function pin name VOUT15 Pin connected with the capacitor (4.7μF) for the regulator VOUT3 Pin connected with the capacitor (4.7μF) for the regulator RVDD5 Power supply pin for the regulator Power supply pin for the digital circuit...
Page 33: Capacitors Between Power Supply Pins
TMPM3V6/M3V4 1.4.1.5 Capacitors between power supply pins Power Supply Power Supply min 10 Power supply line for the analog circuit GND line for the analog circuit Power supply line for the digital circuit GND line for the digital circuit AVSS DVSS AVDD5 DVDD5...
Page 34: The Detail For Pin Names And Function List
Pin names and Functions TMPM3V6/M3V4 1.4.2 Pin names and Function of TMPM3V6/3V4 1.4.2.1 The detail for pin names and function list The mean of the symbol in the table is shown below. 1. Function A The function which is specified without setting of function register is shown in this cell. 2.
Page 35 TMPM3V6/M3V4 1.4.2.2 PORT / Debug pin Table 1-5 Pin names and functions <Sorted by PORT> (1/5) Function B Pin No. Port Specification Function PORT LQFP LQFP64 SMT/ CMOS QFP64 PORT A TB0IN INT3 TB0OUT SCOUT TB1IN INT4 TB1OUT RXIN0 SCLK1 CTS1 TXD1 TB6OUT...
Page 36 Pin names and Functions TMPM3V6/M3V4 Table 1-6 Pin names and functions <Sorted by PORT> (2/5) Pin No. Function B Port Specification Function PORT LQFP LQFP64 SMT/ CMOS QFP64 PORT C SP0DO SDA0/SO0 SP0DI SCL0/SI0 SP0CLK SCK0 SP0FSS UT0TXD50 UT0TXD50 UT0TXD UT0RXD UT0RXD50 PORT D...
Page 37 TMPM3V6/M3V4 Table 1-7 Pin names and functions <Sorted by PORT> (3/5) Function B Pin No. Port Specification Function PORT LQFP LQFP64 SMT/ CMOS QFP64 PORT F TB7IN TB7OUT ALARM PORT G PORT H AIN0 INT0 AIN1 INT1 AIN2 INT2 AIN3 AIN4 AIN5 AIN6...
Page 38 Pin names and Functions TMPM3V6/M3V4 Table 1-8 Pin names and functions <Sorted by PORT> (4/5) Pin No. Function B Port Specification Function PORT LQFP LQFP64 SMT/ CMOS QFP64 PORT I AIN8 AIN9 PORT J AIN10 AIN11 AIN12 AIN13 AIN14 AIN15 AIN16 INTA AIN17...
Page 39 TMPM3V6/M3V4 Table 1-9 Pin names and functions <Sorted by PORT> (5/5) Pin No. Function B Port Specification Function PORT LQFP LQFP64 SMT/ CMOS QFP64 PORT N INTE PORT P Page 17 2019-02-06...
Page 40: Power Supply Pin
Pin names and Functions TMPM3V6/M3V4 1.4.2.3 Control pin Table 1-10 The number of pin and pin names Pin No. Control function LQFP LQFP64 Pin name QFP64 MODE RESET BOOT 1.4.2.4 Power Supply pin Table 1-11 The number of pin and pin names Pin No.
Page 41: Product Information
TMPM3V6/M3V4 2. Product Information This chapter describes peripheral function-related channels or number of units, information of pins and product- specific function information. Use this chapter in conjunction with Chapter Peripheral Function. "2.1 Built-in Functions of the M3V6 and M3V4" "2.2 Information of Each Peripheral Function" "2.2.1 Exception"...
Page 42: Built-In Functions Of The M3V6 And M3V4
Product Information Built-in Functions of the M3V6 and M38V4 TMPM3V6/M3V4 Built-in Functions of the M3V6 and M3V4 The table below shows the differences of the built-in functions between the M3V6 and M3V4. Table 2-1 Functional comparison TMPM3V6FWFG TMPM3V4FWUG/TMPM3V4FSFG Function TMPM3V6FWDFG TMPM3V4FWEFG/TMPM3V4FSEFG LQFP100-P-1414-0.5H (TMPM3V6FWFG) LQFP64-P-1010-0.50E (TMPM3V4FWUG/TMPM3V4FSFG)
Page 43: Information Of Each Peripheral Function
TMPM3V6/M3V4 Information of Each Peripheral Function 2.2.1 Exception 2.2.1.1 Differences of the Interrupt Factors Table 2-2 Differences of the interrupt factors between the M3V6 and M3V4 Interrupt factor M3V6 M3V4 INT6 External interrupt pin 6 INT7 External interrupt pin 7 INTRX2 Serial channel receive interrupt (ch2) INTTX2 Serial channel receive interrupt (ch2) INT9 External interrupt pin 9...
Page 44: 16-Bit Timer / Event Counters (Tmrb)
Product Information Information of Each Peripheral Function TMPM3V6/M3V4 2.2.2 16-bit Timer / Event Counters (TMRB) The TMPM3V6/3V4 incorporates 8-channel TMRB (TMRB0 to 7). External clock input pin/capture trigger input pins (TB3IN and TB5IN), timer flip-flop output pins (TB3OUT and TB5OUT) are not available in Channel 3 (TMRB3) and Channel 5 (TMRB5) of the M3V4. Therefore, the timer functions (counter source clock selection, capture operation, and timer flip-flop output us- ing TB3IN/TB5IN) cannot be used.
Page 45 TMPM3V6/M3V4 Table 2-4 Differences of channels of the TMRB (M3V4) External pin Trigger function between the timers Interrupt Internal connection External clock Transfer TMRB Timer flip-flop Synchronous start Capture in- Channel Capture trigger clock for SIO/ /capture trigger conversion output pin trigger channel terrupt interrupt...
Page 46: Serial Channel (Sio/Uart)
Product Information Information of Each Peripheral Function TMPM3V6/M3V4 2.2.3 Serial Channel (SIO/UART) The M3V6 incorporates three-channel SIO/UART (SIO0,1,2); the M3V4 incorporates two- channel (SIO0,1) SIO/UART. Table 2-5 SIO/UART Pin specifications(M3V6) Pin specification Interrupt Internal connection Channel TXDx RXDx SCLKx CTSx Reception Transmission Transfer clock input...
Page 47: Synchronous Serial Interface (Ssp)
TMPM3V6/M3V4 2.2.6 Synchronous Serial Interface (SSP) TMPM3V6/3V4 incorporates 1 channels of SSP. Table 2-9 SSP pin specifications Pin specification Channel SP0DO SP0DI SP0CLK SP0FSS SSP0 2.2.7 Analog/Digital Converter (ADC) The M3V6 incorporates one unit 18-channel AD converter; the M3V4 incorporates one unit 10-channel AD converter.
Page 48: Debug Interface
Product Information Information of Each Peripheral Function TMPM3V6/M3V4 2.2.8 Debug Interface TMPM3V6/3V4 supports serial wire debug ports, JTAG debug ports and trace outputs. TMPM3V6/3V4 does not support the usage of "JTAG+SW (without TRST)" which is in the "Debug Inter-face" chapter. Table 2-11 Debug pin specifications TRST SWDIO...
Page 49: Processor Core
The TX03 series has a high-performance 32-bit processor core (the Arm Cortex-M3 processor core). For infor- mation on the operations of this processor core, please refer to the "Cortex-M3 Technical Reference Manual" is- sued by Arm Limited.This chapter describes the functions unique to the TX03 series that are not explained in that document.
Page 50: Exceptions/ Interruptions
Processor Core Exceptions/ Interruptions TMPM3V6/M3V4 Exceptions/ Interruptions Exceptions and interruptions are described in the following section. 3.3.1 Number of Interrupt Inputs The number of interrupt inputs can optionally be defined from 1 to 240 in the Cortex-M3 core. TMPM3V6/3V4 has 63/45 interrupt inputs. The number of interrupt inputs is reflected in <INTLINESNUM [4:0]>...
Page 51: Events
TMPM3V6/M3V4 Events The Cortex-M3 core has event output signals and event input signals. An event output signal is output by SEV in- struction execution. If an event is input, the core returns from low-power consumption mode caused by WFE instruc- tion.
Page 52 Processor Core Exclusive access TMPM3V6/M3V4 Page 30 2019-02-06...
Page 53: Memory Map
TMPM3V6/M3V4 4. Memory Map Memory Map The memory maps for TMPM3V6/3V4 are based on the Arm Cortex-M3 processor core memory map. The inter-nal ROM, internal RAM and special function registers (SFR) of TMPM3V6/3V4 are mapped to the Code, SRAM and peripheral regions of the Cortex-M3 respectively. The special function register (SFR) means the control regis-ters of all input/output ports and peripheral functions.
Page 54 Memory Map Memory Map TMPM3V6/M3V4 0xFFFF_FFFF Vendor-Specific Vendor-Specific 0xE010_0000 0xE00F_FFFF CPU Register Reg CPU Register Reg 0xE000_0000 Fault Fault 0x43FF_FFFF Bit Band Alias Bit Band Alias 0x4200_0000 0x41FF_FFFF 0x41FF_F000 Fault Fault 0x400C_3FFF 0x400C_0000 Fault Fault 0x4007_FFFF 0x4000_0000 Fault 0x3F81_FFFF (128KB) Internal ROM (Mirror) 0x3F80_0000...
Page 55 TMPM3V6/M3V4 Vendor-Specific Vendor-Specific CPU Register Reg CPU Register Reg Fault Fault Bit Band Alias Bit Band Alias Fault Fault Fault Fault Fault (64KB) Internal ROM (Mirror) Fault Boot ROM (4KB) (Mirror) Fault Bit Band Alias Bit Band Alias Fault Fault RAM (8KB) RAM (8KB) Fault...
Page 56: Bus Matrix
Memory Map Bus Matrix TMPM3V6/M3V4 Bus Matrix This MCU contains one bus master . Bus masters connect to slave ports (S0 to S2) of Bus Matrix. In the bus matrix, master ports (M0 to M4) con- nect to peripheral functions via connections described as (o) or (・) in the following figure. (・) shows a connec- tion to a mirror area.
Page 57: Structure
TMPM3V6/M3V4 4.2.1 Structure 4.2.1.1 Single chip mode Cortex M3 System Data Instruction Flash ROM Main RAM VLTD BOOT ROM UART SIO/UART I2C/SIO TMRB PORT Figure 4-3 Bus Matrix of TMPM3V6/3V4 Page 35 2019-02-06...
Page 58: Single Boot Mode
Memory Map Bus Matrix TMPM3V6/M3V4 4.2.1.2 Single boot mode Cortex M3 System Data Instruction Flash ROM Main RAM VLTD BOOT ROM UART SIO/UART I2C/SIO TMRB PORT Figure 4-4 Bus Matrix of TMPM3V6/3V4 Page 36 2019-02-06...
Page 59: Connection Table
TMPM3V6/M3V4 4.2.2 Connection table 4.2.2.1 Code area / SRAM area Single chip mode Core Core Core Master S-Bus D-Bus I-Bus Start Address Slave 0x0000_0000 Flash ROM Fault ο ο 0x0002_0000 Fault Fault Fault Fault 0x2000_0000 Main RAM ο Fault Fault 0x2000_2800 Fault Fault...
Page 60 Memory Map Bus Matrix TMPM3V6/M3V4 Single boot mode Core Core Core Master S-Bus D-Bus I-Bus Start Address Slave 0x0000_0000 Boot ROM Fault ο ο 0x0000_1000 Fault Fault Fault Fault 0x2000_0000 Main RAM ο Fault Fault 0x2000_2800 Fault Fault Fault Fault 0x2200_0000 Bit band alias ο...
Page 61: Peripheral Area / External Bus Area
TMPM3V6/M3V4 4.2.2.2 Peripheral area / External bus area Core Core Core Master S-Bus D-Bus I-Bus Start Address Slave 0x4000_0000 PORT ο Fault Fault 0x4001_0000 TMRB ο Fault Fault 0x4002_0000 I2C/SIO ο Fault Fault 0x4002_0080 SIO/UART ο Fault Fault 0x4003_0000 ο Fault Fault 0x4004_0000...
Page 62: Address Lists Of Peripheral Functions
Memory Map Address lists of peripheral functions TMPM3V6/M3V4 Address lists of peripheral functions Do not access to addresses in the peripheral area except control registers. For details of control registers, refer to Chapter of each peripheral functions. Peripheral Function Base Address Port A 0x4000_0000 Port B...
Page 63: Reset Operation
TMPM3V6/M3V4 5. Reset Operation The following are sources of reset operation. ・ Power-on-reset circuit (POR) ・ Voltage Detection Circuit (VLTD) ・ RESET pin (RESET) ・ Watchdog timer (WDT) ・ Oscillation frequency circuit (OFD) ・ Application interrupt by CPU and a signal from the reset register bit <SYSRESETREQ> To recognize a source of reset, check CGRSTFLG in the clock generator register described in Chapter of "...
Page 64: Cold Reset
Reset Operation Cold Reset TMPM3V6/M3V4 Cold Reset When turning-on power, it is necessary to take a stable time of built-in regulator, built-in Flash memory and in- ternal high-speed oscillator into consideration. TMPM3V6/M3V4 has a function to insert a stable time automatically.
Page 65: Reset By Reset Pin
TMPM3V6/M3V4 5.1.2 Reset by RESET pin The reset using the RESET pin will be effective after the power-on counter finishes. And if RESET pin is set to " High " within tPWUP after power-on reset signal becomes " High " , the reset process will be the same as the power-on described in 5.1.1.
Page 66: Warm-Up
Reset Operation Warm-up TMPM3V6/M3V4 Warm-up 5.2.1 Reset Duration To do reset TMPM3V6/3V4, the following condition is required; power supply voltage is in the operational range; RESET pin is kept " Low " at least for 12 system clocks by internal high frequency oscillator. After RE- SET pin becomes "...
Page 67: Clock/Mode Control
TMPM3V6/M3V4 6. Clock/Mode control Outline The clock/mode control block enables to select clock gear, prescaler clock and warm-up of the PLL clock multi- plication circuit and oscillator. There is also the low power consumption mode which can reduce power consumption by mode transitions. This chapter describes how to control clock operating modes and mode transitions.
Page 68: Registers
Clock/Mode control Registers TMPM3V6/M3V4 Registers 6.2.1 Register List The following table shows the CG-related registers and addresses. Base Address = 0x4004_0200 Register name Address (Base+) System control register CGSYSCR 0x0000 Oscillation control register CGOSCCR 0x0004 Standby control register CGSTBYCR 0x0008 PLL selection register CGPLLSEL 0x000C...
Page 69: Cgsyscr (System Control Register)
TMPM3V6/M3V4 6.2.2 CGSYSCR (System control register) Bit symbol After reset Bit symbol FCSTOP SCOSEL After reset Bit symbol FPSEL PRCK After reset Bit symbol GEAR After reset Bit Symbol Type Function 31-24 − Read as "0". − Write "0". 22-21 −...
Page 70: Cgosccr (Oscillation Control Register)
Clock/Mode control Registers TMPM3V6/M3V4 6.2.3 CGOSCCR (Oscillation control register) bit symbol WUODR After reset bit symbol WUODR WUPSEL2 HOSCON OSCSEL XEN2 After reset bit symbol WUODRL XTEN XEN1 After reset bit symbol WUPSEL1 PLLON WUEF WUEON After reset Bit Symbol Type Function 31-20...
Page 71 TMPM3V6/M3V4 Bit Symbol Type Function WUEON Operation of warm-up timer (WUP) 0: don’t care 1: WUP start Enables to start the warm-up timer. Read as "0". Note 1: Refer to Section "6.3.4 Warm-up function" about the Warm-up setup. Note 2: Refer to "6.3.5 Clock Multiplication Circuit (PLL)" about setting PLL. Note 3: If CGOSCCR<OSCSEL>...
Page 72: Cgstbycr (Standby Control Register)
Clock/Mode control Registers TMPM3V6/M3V4 6.2.4 CGSTBYCR (Standby control register) bit symbol After reset bit symbol DRVE After reset bit symbol RXTEN RXEN After reset bit symbol STBY After reset Bit Symbol Type Function 31-20 − Read as "0". 19-17 − Write "0".
Page 73: Cgpllsel (Pll Selection Register)
TMPM3V6/M3V4 6.2.5 CGPLLSEL (PLL Selection Register) bit symbol After reset bit symbol After reset bit symbol After reset bit symbol PLLSEL After reset Bit Symbol Type Function 31-16 − Read as "0". 15-12 − Write "1101" − Read as "0". 10-8 −...
Page 74: Cgcksel (System Clock Selection Register)
Clock/Mode control Registers TMPM3V6/M3V4 6.2.6 CGCKSEL (System clock selection register) bit symbol After reset bit symbol After reset bit symbol After reset bit symbol SYSCK SYSCKFLG After reset Bit Symbol Type Function 31-2 − Read as "0". SYSCK Selects system clock 0: high-speed 1: low-speed Specifies system clock.
Page 75: Clock Control
TMPM3V6/M3V4 Clock control 6.3.1 Clock Type Each clock is defined as follows: : Clock generated by external high-speed oscillator. EHOSC : Clock input from internal high-speed oscillator. IHOSC : Clock generated by external low-speed oscillator. or f specified by CGOSCCR<OSCSEL>. fosc IHOSC EHOSC...
Page 76: Clock System Diagram
Clock/Mode control Clock control TMPM3V6/M3V4 6.3.3 Clock system Diagram Figure 6-1 shows the clock system diagram. The input clocks to selector shown with an arrow are set as default after reset. CGOSCCR<WUEON> CGOSCCR<WUODR[11:0]> CGOSCCR<WUODRL[1:0]> Warming-up timer CGOSCCR <WUPSEL1> AD conversion clock FCSTOP <ADCLK>...
Page 77: Warm-Up Function
TMPM3V6/M3V4 6.3.4 Warm-up function The warm-up function secures the stability time for the oscillator of fs and the PLL with the warm-up tim- er when releasing STOP mode. Refer to "6.6.7 Warm-up" for a detail. How to configure the warm-up function. 1.
Page 78 Clock/Mode control Clock control TMPM3V6/M3V4 The example of warm-up function setup. Table 6-1 The example of warm-up setting (When an external high-speed oscillator is selected) CGOSCCR<WUPSEL1> = "0" : Selects the warm-up clock (Specifies high-speed oscillator). CGOSCCR<WUPSEL2> = "1" : Selects the warm-up clock (Specifies external oscillator (f EHOSC CGOSCCR<WUODR[11:0]>...
Page 79: Clock Multiplication Circuit (Pll)
TMPM3V6/M3V4 6.3.5 Clock Multiplication Circuit (PLL) This circuit outputs the f clock that is multiplied by 4 of the high-speed oscillator output clock (fosc). As a result, the input frequency to oscillator can be low frequency, and the internal clock be made high-speed. 6.3.5.1 How to configure the PLL function The PLL is disabled after reset.
Page 80: The Sequence Of Pll Setting
Clock/Mode control Clock control TMPM3V6/M3V4 6.3.5.2 The sequence of PLL setting The sequence of PLL setting is shown below. The sequence of PLL setting Initial state after releasing reset (Note) PMCR/PMPUP/PMPDN/PMIE = disable CGOSCCR<XEN2> = "1" CGOSCCR<OSCSEL> = "0" CGOSCCR<PLLON= "0" CGPLLSEL<PLLSEL>= "0"...
Page 81: System Clock
TMPM3V6/M3V4 6.3.6 System clock The internal high-speed oscillation clock, the external high-speed oscillation clock or the external low- speed oscillation clock can be used as a source clock of the system clock. Source clock Frequency using PLL 9MHz Internal high-speed oscillation (IHOSC) Can not use PLL (Target) External high-speed oscillation (EHOSC)
Page 82: The Sequence Of System Clock Setting
Clock/Mode control Clock control TMPM3V6/M3V4 6.3.6.1 The sequence of System clock setting The system clock is selected by CGOSCCR. After setting CGOSCCR, the PLL is set by CGPLLSEL and CGOSCCR and the clock gear is set by CGSYSCR. The sequence of PLL setting Initial state after releasing reset PMCR/PMPUP/PMPDN/PMIE = disable CGOSCCR<XEN2>...
Page 83: Prescaler Clock Control
TMPM3V6/M3V4 6.3.7 Prescaler Clock Control Each peripheral function has a prescaler for dividing a clock. As the clock φT0 to be input to each prescal- er, the "fperiph" clock specified in the CGSYSCR<FPSEL[1:0]> can be divided according to the setting in the CGSYSCR<PRCK[2:0]>.
Page 84: Modes And Mode Transitions
Clock/Mode control Modes and Mode Transitions TMPM3V6/M3V4 Modes and Mode Transitions 6.4.1 Mode Transitions The NORMAL mode and the SLOW mode use the high-speed and low-speed clocks for the system clock re- spectively. The IDLE, SLEEP and STOP modes can be used as the low power consumption mode that enables to re- duce power consumption by halting processor core operation.
Page 85: Operation Mode
TMPM3V6/M3V4 Operation mode Two operation modes, NORMAL and SLOW, are available. The features of each mode are described below. 6.5.1 NORMAL mode This mode is to operate the CPU core and the peripheral hardware by using the high-speed clock. It is shifted to the NORMAL mode after reset. The low-speed clock can also be oscillated. 6.5.2 SLOW mode This mode is to operate the CPU core and the peripheral hardware by using the low-speed clock with high-...
Page 86: Low Power Consumption Modes
Clock/Mode control Low Power Consumption Modes TMPM3V6/M3V4 Low Power Consumption Modes The TMPM3V6/M3V4 has the low power consumption modes: IDLE, SLEEP and STOP. To shift to the low pow-er consumption mode, specify the mode in the system control register CGSTBYCR<STBY[2:0]> and execute the WFI (Wait For Interrupt) instruction.
Page 87 TMPM3V6/M3V4 6.6.3 STOP mode Except some peripheral circuits, all the internal circuits including the internal oscillator are brought to a stop in STOP mode. When releasing STOP mode, the operation mode changes to the operation mode before entering STOP mode. The STOP mode enables to select the pin status by setting the CGSTBYCR<DRVE>.
Page 88 Clock/Mode control Low Power Consumption Modes TMPM3V6/M3V4 6.6.4 Low power Consumption Mode Setting The low power consumption mode is specified by the setting of the standby control register CGSTBYCR<STBY[2:0]>. Table 6-5 shows the mode setting in the <STBY[2:0]>. Table 6-5 Low power consumption mode setting CGSTBYCR Mode <STBY[2:0]>...
Page 89 TMPM3V6/M3V4 6.6.5 Operational Status in Each Mode Table 6-6 show the operational status in each mode. Table 6-6 Operational Status in Each Mode Block NORMAL IDLE SLOW SLEEP STOP Processor core ο × ο × × I/O port ο ο ο...
Page 90 Clock/Mode control Low Power Consumption Modes TMPM3V6/M3V4 6.6.6 Releasing the Low Power Consumption Mode The low power consumption mode can be released by an interrupt request, Non-Maskable Interrupt (NMI) or reset. The release source that can be used is determined by the low power consumption mode selected. Details are shown in Table 6-7.
Page 91 TMPM3V6/M3V4 ・ Release by interrupt request To release the low power consumption mode by an interrupt, the interrupt is set to detect inter- rupt request before entering the low power consumption mode. Regarding to setting the interrupt to be used to release the STOP mode, refer to "Exceptions". ・...
Page 92 Clock/Mode control Low Power Consumption Modes TMPM3V6/M3V4 6.6.7 Warm-up Mode transition may require the warm-up so that the oscillator provides stable oscillation. In the mode transition from STOP to the NORMAL/SLOW or from SLEEP to NORMAL, the warm-up coun- ter and the internal oscillator are activated automatically. And then the system clock output is started after the elapse of warm-up time.
Page 93 TMPM3V6/M3V4 6.6.8 Clock Operations in Mode Transition The clock operations in mode transition are described as follows. 6.6.8.1 Transition of operation modes: NORMAL → STOP → NORMAL When returning to the NORMAL mode from the STOP mode, the warm-up is activated automatically. The CGOSCCR<WUODR[11:0]>...
Page 94 Clock/Mode control Low Power Consumption Modes TMPM3V6/M3V4 6.6.8.2 Transition of operation modes: NORMAL → SLEEP → NORMAL When returning to the NORMAL mode from the SLEEP mode, the warm-up is activated automatically. The CGOSCCR<WUODR[11:0]> and <WUODRL[1:0]> are set to the stable time of an external low- speed oscillator.
Page 95 TMPM3V6/M3V4 6.6.8.3 Transition of operation modes: SLOW → STOP → SLOW When returning to the SLOW mode from the STOP mode, the warm-up is activated automatically. The CGOSCCR<WUODR[11:0]> and <WUODRL[1:0]> are set to the stable time of an external low- speed oscillator.
Page 96 Clock/Mode control Low Power Consumption Modes TMPM3V6/M3V4 6.6.9 Precaution on Transition to the Low-power Consumption Mode 6.6.9.1 Case when the MCU Enters IDLE, SLEEP or STOP Mode When the WFI instruction is executed to enter IDLE mode, SLEEP mode or STOP mode, if an interrupt request for release from the low-power consumption mode occurs, the MCU does not enter IDLE mode, SLEEP mode or STOP mode.
Page 97 TMPM3V6/M3V4 7. Exceptions This chapter describes features, types and handling of exceptions. Exceptions have close relation to the CPU core. Refer to "Cortex-M3 Technical Reference Manual" if needed. Overview An exception causes the CPU to stop the currently executing process and handle another process. There are two types of exceptions: those that are generated when some error condition occurs or when an instruc- tion to generate an exception is executed;...
Page 98 Exceptions Overview TMPM3V6/M3V4 7.1.2 Handling Flowchart The following shows how an exception/interrupt is handled. In the following descriptions, indicates hardware handling. Indicates software handling. Each step is described later in this chapter. Processing Description Detection by The CG/CPU detects the exception request. Section 7.1.2.1 CG/CPU Handling by CPU...
Page 99 TMPM3V6/M3V4 7.1.2.1 Exception Request and Detection Exception occurrence Exception sources include instruction execution by the CPU, memory accesses, and interrupt re- quests from external interrupt pins or peripheral functions. An exception occurs when the CPU executes an instruction that causes an exception or when an er- ror condition occurs during instruction execution.
Page 100 Exceptions Overview TMPM3V6/M3V4 Priority setting ・ Priority levels The external interrupt priority is set to the interrupt priority register and other exceptions are set to <PRI_n> bit in the system handler priority register. The configuration <PRI_n> can be changed, and the number of bits required for setting the priority varies from 3 bits to 8 bits depending on products.
Page 101 TMPM3V6/M3V4 Stacking When the CPU detects an exception, it pushes the contents of the following eight registers to the stack in the following order: ・ Program Counter (PC) ・ Program Status Register (xPSR) ・ r0 - r3 ・ r12 ・ Link Register (LR) The SP is decremented by eight words by the completion of the stack push.The following shows the state of the stack after the register contents have been pushed.
Page 102 Exceptions Overview TMPM3V6/M3V4 Late-arriving If the CPU detects a higher priority exception before executing the ISR for a previous exception, the CPU handles the higher priority exception first. This is called "late-arriving". A late-arriving exception causes the CPU to fetch a new vector address for branching to the corre- sponding ISR, but the CPU does not newly push the register contents to the stack.
Page 103 TMPM3V6/M3V4 7.1.2.4 Exception exit Execution after returning from an ISR When returning from an ISR, the CPU takes one of the following actions: ・ Tail-chaining If a pending exception exists and there are no stacked exceptions or the pending excep- tion has higher priority than all stacked exceptions, the CPU returns to the ISR of the pend- ing exception.
Page 104 Exceptions Reset Exceptions TMPM3V6/M3V4 Reset Exceptions Reset exceptions are generated from the following five sources. Use the Reset Flag (CGRSTFLG) Register of the Clock Generator to identify the source of a reset. ・ External reset pin A reset exception occurs when an external reset pin changes from "Low" to "High". ・...
Page 105 TMPM3V6/M3V4 SysTick SysTick provides interrupt features using the CPU's system timer. When you set a value in the SysTick Reload Value Register and enable the SysTick features in the SysTick Con- trol and Status Register, the counter loads with the value set in the Reload Value Register and begins counting down.When the counter reaches "0", a SysTick exception occurs.You may be pending exceptions and use a flag to know when the timer reaches "0".
Page 106 Exceptions Interrupts TMPM3V6/M3V4 Interrupts This chapter describes routes, sources and required settings of interrupts. The CPU is notified of interrupt requests by the interrupt signal from each interrupt source. It sets priority on interrupts and handles an interrupt request with the highest priority. Interrupt requests for clearing a standby mode are notified to the CPU via the clock generator.
Page 107 TMPM3V6/M3V4 7.5.1.2 Generation An interrupt request is generated from an external pin or peripheral function assigned as an interrupt source or by setting the NVIC's Interrupt Set-Pending Register. ・ From external pin Set the port control register so that the external pin can perform as an interrupt function pin. ・...
Page 108 Exceptions Interrupts TMPM3V6/M3V4 7.5.1.5 List of Interrupt Sources Table 7-3 shows the list of interrupt sources. Table 7-3 Lists of Interrupt Sources The active level to release the low power consump- CG interrupt tion mode mode Interrupt Source "Low" "High" Rising Falling Both...
Page 109 TMPM3V6/M3V4 Table 7-3 Lists of Interrupt Sources The active level to release the low power consump- CG interrupt tion mode mode Interrupt Source "Low" "High" Rising Falling Both control register edge edge edge level level INTCAP51 16-bit TMRB input capture 1 (channel 5) INT6 External interrupt pin 6 ο...
Page 110 Exceptions Interrupts TMPM3V6/M3V4 Table 7-3 Lists of Interrupt Sources The active level to release the low power consump- CG interrupt tion mode mode Interrupt Source "Low" "High" Rising Falling Both control register edge edge edge level level INTC External interrupt pin C ο...
Page 111 TMPM3V6/M3V4 7.5.2 Interrupt Handling 7.5.2.1 Flowchart The following shows how an interrupt is handled. In the following descriptions, indicates hardware handling. indicates software handling. Processing Details Set the relevant NVIC registers for detecting interrupts. Set the clock generator as well if each interrupt source is used to clear a stand- by mode.
Page 112 Exceptions Interrupts TMPM3V6/M3V4 Processing Details Program for the ISR. ISR execution Clear the interrupt source if needed. "7.5.2.6 Interrupt Service Routine (ISR)" Return to preceding program Configure to return to the preceding program of the ISR. Page 90 2019-02-06...
Page 113 TMPM3V6/M3V4 7.5.2.2 Preparation When preparing for an interrupt, you need to pay attention to the order of configuration to avoid any un- expected interrupt on the way. Initiating an interrupt or changing its configuration must be implemented in the following order basical- ly.
Page 114 Exceptions Interrupts TMPM3V6/M3V4 You can assign grouping priority by using the PRIGROUP field in the Application Interrupt and Re- set Control Register. NVIC register <PRI_n> ← "priority" <PRIGROUP> ← "group priority"(This is configurable if required.) Note:"n" indicates the corresponding exceptions/interrupts. This product uses three bits for assigning a priority level.
Page 115 TMPM3V6/M3V4 Interrupt requests from external pins can be used without setting the clock generator if they are not used for exiting a standby mode. However, an "High" pulse or "High"-level signal must be in- put so that the CPU can detect it as an interrupt request. Also, be aware of the description of"7.5.1.4 Precautions when using external interrupt pins".
Page 116 Exceptions Interrupts TMPM3V6/M3V4 7.5.2.4 Detection by CPU The CPU detects an interrupt request with the highest priority. 7.5.2.5 CPU processing On detecting an interrupt, the CPU pushes the contents of PC, PSR, r0-r3, r12 and LR to the stack then enter the ISR.
Page 117 TMPM3V6/M3V4 Exception/Interrupt-Related Registers The CPU's NVIC registers and clock generator registers described in this chapter are shown below with their re- spective addresses. 7.6.1 Register List NVIC registers Base Address = 0xE000_E000 Register name Address(Base+) SysTick Control and Status Register 0x0010 SysTick Reload Value Register 0x0014...
Page 118 Exceptions Exception/Interrupt-Related Registers TMPM3V6/M3V4 7.6.2 NVIC Registers 7.6.2.1 SysTick Control and Status Register bit symbol After reset bit symbol COUNTFLAG After reset bit symbol After reset bit symbol CLKSOURCE TICKINT ENABLE After reset Bit Symbol Type Function 31-17 − Read as 0. COUNTFLAG 0: Timer not counted to 0 1: Timer counted to 0...
Page 119 TMPM3V6/M3V4 7.6.2.2 SysTick Reload Value Register bit symbol After reset bit symbol RELOAD After reset Undefined bit symbol RELOAD After reset Undefined bit symbol RELOAD After reset Undefined Bit Symbol Type Function 31-24 − Read as 0. 23-0 RELOAD Reload value Set the value to load into the SysTick Current Value Register when the timer reaches "0".
Page 120 Exceptions Exception/Interrupt-Related Registers TMPM3V6/M3V4 7.6.2.4 SysTick Calibration Value Register bit symbol NOREF SKEW After reset bit symbol TENMS After reset bit symbol TENMS After reset bit symbol TENMS After reset Bit Symbol Type Function NOREF 0: Reference clock provided 1: No reference clock SKEW 0: Calibration value is 10 ms.
Page 121 TMPM3V6/M3V4 7.6.2.5 Interrupt Control Registers Each interrupt source has the interrupt set-enable register, interrupt clear-enable register, interrupt set-pending register and interrupt clear-pending register. Each bit corresponds to each interrupt source. Interrupt Set-Enable Register This register enables interrupts and identifies whether the interrupt is enabled/disabled. When set this register to "1", the corresponding interrupt is enabled.
Page 122 Exceptions Exception/Interrupt-Related Registers TMPM3V6/M3V4 Interrupt Set-Enable Register 1 SETENA SETENA SETENA SETENA SETENA SETENA Bit symbol (Interrupt 31) (Interrupt 30) (Interrupt 27) (Interrupt 26) (Interrupt 25) (Interrupt 24) After reset SETENA SETENA SETENA SETENA SETENA SETENA Bit symbol (Interrupt 23 (Interrupt 22) (Interrupt 21) (Interrupt 20)
Page 123 TMPM3V6/M3V4 Interrupt Set-Enable Register 3 Bit symbol After reset Bit symbol After reset SETENA SETENA SETENA SETENA SETENA SETENA Bit symbol (Interrupt 77) (Interrupt 76) (Interrupt 75) (Interrupt 74) (Interrupt 73) (Interrupt 72) After reset SETENA SETENA SETENA SETENA SETENA SETENA Bit symbol (Interrupt 71)
Page 124 Exceptions Exception/Interrupt-Related Registers TMPM3V6/M3V4 Interrupt Clear-Enable Register This register disables interrupts and identifies whether the interrupt is enabled/disabled. When set this register to "1", the corresponding interrupt is disabled. Writing "0" has no meaning. When this register is read, whether the corresponding interrupt is enabled or disabled is identified. Bit symbol Type Function...
Page 125 TMPM3V6/M3V4 Interrupt Clear-Enable Register 1 CLRENA CLRENA CLRENA CLRENA CLRENA CLRENA Bit symbol (Interrupt 31) (Interrupt 30) (Interrupt 27) (Interrupt 26) (Interrupt 25) (Interrupt 24) After reset CLRENA CLRENA CLRENA CLRENA CLRENA CLRENA Bit symbol (Interrupt 23 (Interrupt 22) (Interrupt 21) (Interrupt 20) (Interrupt 19) (Interrupt 17)
Page 126 Exceptions Exception/Interrupt-Related Registers TMPM3V6/M3V4 Interrupt Clear-Enable Register 3 Bit symbol After reset Bit symbol After reset CLRENA CLRENA CLRENA CLRENA CLRENA CLRENA Bit symbol (Interrupt 77) (Interrupt 76) (Interrupt 75) (Interrupt 74) (Interrupt 73) (Interrupt 72) After reset CLRENA CLRENA CLRENA CLRENA CLRENA...
Page 127 TMPM3V6/M3V4 Interrupt Set-Pending Register This register forcibly suspends interrupts and identifies whether interrupts are suspended. When this register is set to "1", the corresponding interrupt is suspended. However, this register is in-valid for the interrupt which has already been suspended or disabled. Writing "0"...
Page 128 Exceptions Exception/Interrupt-Related Registers TMPM3V6/M3V4 Interrupt Set-Pending Register 1 SETPEND SETPEND SETPEND SETPEND SETPEND SETPEND Bit symbol (Interrupt 31) (Interrupt 30) (Interrupt 27) (Interrupt 26) (Interrupt 25) (Interrupt 24) After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined SETPEND SETPEND SETPEND SETPEND SETPEND...
Page 129 TMPM3V6/M3V4 Interrupt Set-Pending Register 3 Bit symbol After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Bit symbol After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined SETPEND SETPEND SETPEND SETPEND SETPEND SETPEND Bit symbol (Interrupt 77) (Interrupt 76) (Interrupt 75) (Interrupt 74) (Interrupt 73)
Page 130 Exceptions Exception/Interrupt-Related Registers TMPM3V6/M3V4 Interrupt Clear-Pending Register This register clears pending interrupts and identifies whether interrupts are suspended. When set this register to "1", the corresponding pending interrupt is cleared. However, this regis- ter is invalid for the interrupt which has already been started. Writing "0"...
Page 131 TMPM3V6/M3V4 Interrupt Clear-Pending Register 1 CLRPEND CLRPEND CLRPEND CLRPEND CLRPEND CLRPEND Bit symbol (Interrupt 31) (Interrupt 30) (Interrupt 27) (Interrupt 26) (Interrupt 25) (Interrupt 24) After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined CLRPEND CLRPEND CLRPEND CLRPEND CLRPEND CLRPEND Bit symbol (Interrupt 23...
Page 132 Exceptions Exception/Interrupt-Related Registers TMPM3V6/M3V4 Interrupt Clear-Pending Register 3 Bit symbol After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Bit symbol After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined CLRPEND CLRPEND CLRPEND CLRPEND CLRPEND CLRPEND Bit symbol (Interrupt 77) (Interrupt 76) (Interrupt 75)
Page 133 TMPM3V6/M3V4 7.6.2.6 Interrupt Priority Register Each interrupt is provided with eight bits of an Interrupt Priority Register. The following shows the addresses of the Interrupt Priority Registers corresponding to interrupt numbers. 24 23 16 15 0xE000_E400 PRI_3 PRI_2 PRI_1 PRI_0 0xE000_E404 PRI_7 PRI_6...
Page 134 Exceptions Exception/Interrupt-Related Registers TMPM3V6/M3V4 Bit Symbol Type Function 31-29 PRI_3 Priority of interrupt number 3 28-24 − Read as 0. 23-21 PRI_2 Priority of interrupt number 2 20-16 − Read as 0. 15-13 PRI_1 Priority of interrupt number 1 12-8 −...
Page 135 TMPM3V6/M3V4 7.6.2.7 Vector Table Offset Register bit symbol TBLBASE TBLOFF After reset bit symbol TBLOFF After reset bit symbol TBLOFF After reset bit symbol TBLOFF After reset Bit Symbol Type Function 31-30 − Read as 0. TBLBASE Table base The vector table is in: 0: Code space 1: SRAM space 28-7...
Page 136 Exceptions Exception/Interrupt-Related Registers TMPM3V6/M3V4 7.6.2.8 Application Interrupt and Reset Control Register bit symbol VECTKEY/VECTKEYSTAT After reset bit symbol VECTKEY/VECTKEYSTAT After reset bit symbol ENDIANESS PRIGROUP After reset SYSRESET VECTCLR bit symbol VECTRESET ACTIVE After reset Bit Symbol Type Function 31-16 VECTKEY Register key (Write)/...
Page 137 TMPM3V6/M3V4 7.6.2.9 System Handler Priority Register Each exception is provided with eight bits of a System Handler Priority Register. The following shows the addresses of the System Handler Priority Registers corresponding to each excep- tion. 24 23 16 15 PRI_7 PRI_6 PRI_5 PRI_4...
Page 138 Exceptions Exception/Interrupt-Related Registers TMPM3V6/M3V4 7.6.2.10 System Handler Control and State Register bit symbol After reset USGFAULT BUSFAULT MEMFAULT bit symbol After reset SVCALL BUSFAULT MEMFAULT USGFAULT MONITOR bit symbol SYSTICKACT PENDSVACT PENDED PENDED PENDED PENDED After reset USGFAULT BUSFAULT MEMFAULT bit symbol SVCALLACT After reset...
Page 139 TMPM3V6/M3V4 Bit Symbol Type Function USGFAULT Usage Fault 0: Inactive 1: Active − Read as 0. BUSFAULT Bus Fault 0: Inactive 1: Active MEMFAULT Memory Management 0: Inactive 1: Active Note: You must clear or set the active bits with extreme caution because clearing and setting these bits does not repair stack contents.
Page 140 Exceptions Exception/Interrupt-Related Registers TMPM3V6/M3V4 7.6.3 Clock Generator Registers 7.6.3.1 CG Interrupt Mode Control Register This CG interrupt mode control register specifies the active level to release the low power consump- tion mode and enables/disables the releasing low power consumption mode. A detected active level can al- so be read from this register.
Page 141 TMPM3V6/M3V4 Table 7-4 The Active Level to release low-power consumption mode The active level to release the low-power consump- tion mode Active level Interrupt factor setting register "Low" "High" Rising Falling Both edge edge edge level level CGIMCGA INT0 External interrupt pin 0 ο...
Page 142 Exceptions Exception/Interrupt-Related Registers TMPM3V6/M3V4 CGIMCGA (CG Interrupt Mode Control Register A) Bit symbol EMCG3 EMST3 INT3EN After reset undefined Bit symbol EMCG2 EMST2 INT2EN After reset undefined Bit symbol EMCG1 EMST1 INT1EN After reset undefined Bit symbol EMCG0 EMST0 INT0EN After reset undefined Note 1: The active level specified by <EMCGx[2:0]>...
Page 143 TMPM3V6/M3V4 CGIMCGC(CG Interrupt Mode Control Register C) Bit symbol EMCGB EMSTB INTBEN After reset undefined Bit symbol EMCGA EMSTA INTAEN After reset undefined Bit symbol EMCG9 EMST9 INT9EN After reset undefined Bit symbol EMCG8 EMST8 INT8EN After reset undefined Note 1: The active level specified by <EMCGx[2:0]> varies depending on the interrupt request. Refer to Table 7-4. Note 2: <EMSTx>...
Page 144 Exceptions Exception/Interrupt-Related Registers TMPM3V6/M3V4 CGIMCGE(CG Interrupt Mode Control Register E) Bit symbol After reset undefined Bit symbol After reset undefined Bit symbol EMCGRMCRX EMSTRMCRX TRMCRXEN After reset undefined Bit symbol EMCGRTC EMSTRTC INTRTCEN After reset undefined Note 1: The active level specified by <EMCGx[2:0]> varies depending on the interrupt request. Refer to Table 7-4. Note 2: <EMSTx>...
Page 145 TMPM3V6/M3V4 7.6.3.2 CGICRCG(CG Interrupt Request Clear Register) Bit symbol After reset Bit symbol After reset Bit symbol After reset Bit symbol ICRCG After reset Bit symbol Type Function 31-5 − Read as "0". ICRCG[4:0] Clear interrupt requests. 0_0000: INT0 0_1000: INT8 1_0000: INTRTC 0_0001: INT1 0_1001: INT9...
Page 146 Exceptions Exception/Interrupt-Related Registers TMPM3V6/M3V4 7.6.3.3 CGNMIFLG(NMI Flag Register) bit symbol After reset bit symbol After reset bit symbol After reset bit symbol NMIFLG0 After reset Bit Symbol Type Function 31-3 − Read as 0. − Reads as undefined. NMIFLG0 NMI source generation flag 0: not applicable 1: generated from WDT Note:<NMIFLG>...
Page 147 TMPM3V6/M3V4 7.6.3.4 CGRSTFLG (Reset Flag Register) bit symbol After power-on reset bit symbol After power-on reset bit symbol After power-on reset bit symbol OFDRSTF DBGRSTF VLTDRSTF WDTRSTF PINRSTF PONRSTF After power-on reset Bit Symbol Type Function 31-6 − Read as 0. OFDRSTF OFD reset flag 0: "0"...
Page 148 Exceptions Exception/Interrupt-Related Registers TMPM3V6/M3V4 Page 126 2019-02-06...
Page 149 TMPM3V6/M3V4 8. Digital Noise Filter Circuit (DNF) The digital noise canceler circuit can eliminate noise of input signals from external interrupt pins at the certain range. Configuration Digital noise filter circuit Noise filter circuit NFENCR<NFEN0> External INT0 interrupt request interrupt pin (INT0) Filtering NFCKCR<NFCKS>...
Page 150 Digital Noise Filter Circuit (DNF) Registers TMPM3V6/M3V4 Registers 8.2.1 Register List Base Address = 0x4006_0000 Register name Address(Base+) Noise filter control register NFCKCR 0x0000 Noise filter enable register NFENCR 0x0004 Page 128 2019-02-06...
Page 151 TMPM3V6/M3V4 8.2.1.1 NFCKCR (Noise Filter Control Register) bit symbol After reset bit symbol After reset bit symbol After reset bit symbol NFCKS After reset Bit Symbol Type Function 31-3 − Read as "0". NFCKS[2:0] Noise filter clock selection 000: Clock control circuit stops 001: fsys/2 clock output 010: fsys/4 clock output 011: fsys/8 clock output...
Page 152 Digital Noise Filter Circuit (DNF) Registers TMPM3V6/M3V4 8.2.1.2 NFENCR (Noise Filter Enable register) bit symbol After reset bit symbol After reset bit symbol NFENF NFENE NFEND NFENC NFENB NFENA NFEN9 NFEN8 After reset bit symbol NFEN7 NFEN6 NFEN5 NFEN4 NFEN3 NFEN2 NFEN1 NFEN0...
Page 153 TMPM3V6/M3V4 Bit Symbol Type Function NFEN3 INT3 noise filter is enabled/disabled. 0: Disabled 1: Enabled NFEN2 INT2 noise filter is enabled/disabled. 0: Disabled 1: Enabled NFEN1 INT1 noise filter is enabled/disabled. 0: Disabled 1: Enabled NFEN0 INT0 noise filter is enabled/disabled. 0: Disabled 1: Enabled Note: Disabled (Pre-noise filtering output signal and noise filter circuit counter are cleared when releasing...
Page 154 Digital Noise Filter Circuit (DNF) Operation Description TMPM3V6/M3V4 Operation Description 8.3.1 Configuration The noise filter circuit consists of the noise filter circuit and interrupt request generation circuit. It eliminates high level or low level noise from external inputs and then CG detects the rising/falling edge or signal level (high or low) to determine the signal state in each interrupt signal.
Page 155 TMPM3V6/M3V4 9. Input / Output port This chapter describes port-related registers, their setting and circuits. Registers When the port registers are used, the following registers must be set. All registers are 32-bits. The configurations are different depend on the number of port bits and assignation of the function.
Page 156 Input / Output port Registers TMPM3V6/M3V4 9.1.1 Register list For detail of the base address, refer to "Address lists of peripheral functions" of "Memory Map" chapter. Address Register name PORT A PORT B PORT C PORT D PORT E (Base+) Data register 0x0000 PADATA...
Page 157 TMPM3V6/M3V4 9.1.2 Port function and setting list The list of the function and setting register for each port is shown belows: "Table 9-1 PORT A Setting List" "Table 9-2 PORT B Setting List" "Table 9-3 PORT C Setting List" "Table 9-4 PORT D Setting List" "Table 9-5 PORT E Setting List"...
Page 158 Input / Output port Registers TMPM3V6/M3V4 9.1.2.1 PORT A Table 9-1 PORT A Setting List Reset status Control registers PORT Input/Output Type PADATA PACR PAFRn PAOD PAPUP PAPDN PAIE After reset Input Port Input Output Port Output TB0IN Input PAFR1 INT3 Input PAFR2...
Page 159 TMPM3V6/M3V4 9.1.2.2 PORT B Table 9-2 PORT B Setting List Reset status Control registers PORT Input/Output Type PBDATA PBCR PBFRn PBOD PBPUP PBPDN PBIE After reset Input Port Input Output Port Output TRACECLK Output PBFR1 After reset Input Port Input Output Port Output TRACEDATA0...
Page 160 Input / Output port Registers TMPM3V6/M3V4 9.1.2.3 PORT C Table 9-3 PORT C Setting List Reset status Control registers PORT Input/Output Type PCDATA PCCR PCFRn PCOD PCPUP PCPDN PCIE After reset Input Port Input Output Port Output SP0DO Output PCFR2 Output PCFR3 SDA0...
Page 161 TMPM3V6/M3V4 9.1.2.4 PORT D Table 9-4 PORT D Setting List Reset status Control registers PORT Input/Output Type PDDATA PDCR PDFRn PDOD PDPUP PDPDN PDIE After reset Input Port Input Output Port Output TB5IN Input PDFR2 INTC Input PDFR3 After reset Input Port Input Output Port...
Page 162 Input / Output port Registers TMPM3V6/M3V4 9.1.2.5 PORT E Table 9-5 PORT E Setting List Reset status Control registers PORT Input/Output Type PEDATA PECR PEFRn PEOD PEPUP PEPDN PEIE After reset Input Port Input Output Port Output TXD0 Output PEFR1 After reset Input Port Input...
Page 163 TMPM3V6/M3V4 9.1.2.6 PORT F Table 9-6 PORT F Setting List Reset status Control registers PORT Input/Output Type PFDATA PFCR PFFRn PFOD PFPUP PFPDN PFIE After reset Input Port Input Output Port Output TB7IN Input PFFR1 After reset Input Port Input Output Port Output TB7OUT...
Page 164 Input / Output port Registers TMPM3V6/M3V4 9.1.2.7 PORT G Table 9-7 PORT G Setting List Reset status Control registers PORT Input/Output Type PGDATA PGCR PGFRn PGOD PGPUP PGPDN PGIE After reset Input Port Input Output Port Output After reset Input Port Input Output Port Output...
Page 165 TMPM3V6/M3V4 9.1.2.8 PORT H Table 9-8 PORT H Setting List Reset status Control registers PORT Input/Output Type PHDATA PHCR PHFRn PHOD PHPUP PHPDN PHIE After reset Input Port Input Output Port Output INT0 Input PHFR1 AIN0 Input After reset Input Port Input Output Port Output...
Page 166 Input / Output port Registers TMPM3V6/M3V4 9.1.2.9 PORT I Table 9-9 PORT I Setting List Reset status Control registers PORT Input/Output Type PIDATA PICR PIFRn PIOD PIPUP PIPDN PIIE After reset Input Port Input Output Port Output AIN8 Input After reset Input Port Input Output Port...
Page 167 TMPM3V6/M3V4 9.1.2.10 PORT J Table 9-10 PORT J Setting List Reset status Control registers PORT Input/Output Type PJDATA PJCR PJFRn PJOD PJPUP PJPDN PJIE After reset Input Port Input Output Port Output AIN10 Input After reset Input Port Input Output Port Output AIN11 Input...
Page 168 Input / Output port Registers TMPM3V6/M3V4 9.1.2.11 PORT L Table 9-11 PORT L Setting List Reset status Control registers PORT Input/Output Type PLDATA PLCR PLFRn PLOD PLPUP PLPDN PLIE After reset Input Port Input Output Port Output 0 (Note1) After reset Input Port Input Output Port...
Page 169 TMPM3V6/M3V4 9.1.2.12 PORT M Table 9-12 PORT M Setting List Reset status Control registers PORT Input/Output Type PMDATA PMCR PMFRn PMOD PMPUP PMPDN PMIE After reset Input Port Input Output Port Output Input After reset Input Port Input Output Port Output Output Page 147...
Page 170 Input / Output port Registers TMPM3V6/M3V4 9.1.2.13 PORT N Table 9-13 PORT N Setting List Reset status Control registers PORT Input/Output Type PNDATA PNCR PNFRn PNOD PNPUP PNPDN PNIE After reset Input Port Input Output Port Output After reset Input Port Input Output Port Output...
Page 171 TMPM3V6/M3V4 9.1.2.14 PORT P Table 9-14 PORT P Setting List Reset status Control registers PORT Input/Output Type PPDATA PPCR PPFRn PPOD PPPUP PPPDN PPIE After reset Input Port Input Output Port Output Input After reset Input Port Input Output Port Output Output Page 149...
Page 172 Input / Output port Block Diagrams of Ports TMPM3V6/M3V4 Block Diagrams of Ports The ports are classified as shown below. Please refer to the following pages for the block diagrams of each port type. Dot lines in the figure indicate the part of the equivalent circuit described in the "Block diagrams of ports". 9.2.1 Type FT1 RESET...
Page 173 TMPM3V6/M3V4 9.2.2 Type FT2 Power-On Reset Drive Disable in STOP Mode PxPUP (Pull-up Control) PxPDN (Pull-down Control) PxCR (Output Control) Function Output Enable PxFRn (Function Control) Function Output PxDATA Port (Output Latch) PxOD (Open Drain Control) PxIE (Input Control) Port Read Function Input Figure 9-2 Port Type FT2...
Page 174 Input / Output port Block Diagrams of Ports TMPM3V6/M3V4 9.2.3 Type FT3 RESET Power-On Reset Drive Disable in STOP Mode PxPUP (Pull-up Control) PxPDN (Pull-down Control) PxCR (Output Control) Function Output Enable PxFRn (Function Control) Function Output PxDATA Port (Output Latch) PxOD (Open Drain Control)
Page 175 TMPM3V6/M3V4 9.2.4 Type FT4 RESET Power-On Reset Drive Disable in STOP Mode PxPUP (Pull-up Control) PxPDN (Pull-down Control) PxCR (Output Control) PxFRn (Function Control) PxDATA (Output Latch) Port PxOD (Open Drain Control) PxIE (Input Control) Port Read Function Noise Filter Input (30ns Typ) Figure 9-4 Port Type FT4...
Page 176 Input / Output port Block Diagrams of Ports TMPM3V6/M3V4 9.2.5 Type FT5 RESET Power-On Reset Drive Disable in STOP Mode PxPUP (Pull-up Control) PxPDN (Pull-down Control) PxCR (Output Control) PxDATA (Output Latch) Port PxOD (Open Drain Control) PxIE (Input Control) Port Read AINn Figure 9-5 Port Type FT5...
Page 177 TMPM3V6/M3V4 9.2.6 Type FT6 RESET Power-On Reset Drive Disable in STOP Mode PxPUP (Pull-up Control) PxPDN (Pull-down Control) PxCR (Output Control) PxDATA (Output Latch) Port PxOD (Open Drain Control) BOOT Figure 9-6 Port Type FT6 Page 155 2019-02-06...
Page 178 Input / Output port Block Diagrams of Ports TMPM3V6/M3V4 Page 156 2019-02-06...
Page 179 TMPM3V6/M3V4 10. 16-bit Timer / Event Counters (TMRB) 10.1 Outline TMRB operate in the following four operation modes: ・ 16-bit interval timer mode ・ 16-bit event counter mode ・ 16-bit programmable pulse generation mode (PPG) ・ External trigger programmable pulse generation mode (PPG) ・...
Page 180 16-bit Timer / Event Counters (TMRB) 10.2 Differences in the Specifications TMPM3V6/M3V4 10.2 Differences in the Specifications Each channel functions independently and the channels operate in the same way except for the differences in their specification as shown in Table 10-1. Some of the channels can put the capture trigger and the synchronous start trigger on other channels.
Page 181 TMPM3V6/M3V4 10.3 Configuration Each channel consists of a 16-bit up-counter, two 16-bit timer registers (double-buffered), two 16-bit capture reg- isters, two comparators, a capture input control, a timer flip-flop and its associated control circuit.Timer operation modes and the timer flip-flop are controlled by a register. Register 1 interrupt output Register 0 interrupt output Overflow interrupt output...
Page 182 16-bit Timer / Event Counters (TMRB) 10.4 Registers TMPM3V6/M3V4 10.4 Registers 10.4.1 Register list according to channel The followings are the TMRB control registers and addresses. For detail of the base address, refer to "Address lists of peripheral functions" of "Memory Map" chapter. Register name Address (Base+) Enable register...
Page 183 TMPM3V6/M3V4 10.4.2 TBxEN (Enable register) bit symbol After reset bit symbol After reset bit symbol After reset bit symbol TBEN TBHALT After reset Bit Symbol Type Function 31-8 − Read as "0". TBEN TMRBx operation 0: Disable 1: Enable Specifies the TMRB operation. When the operation is disabled, no clock is supplied to the other registers in the TMRB module.
Page 184 16-bit Timer / Event Counters (TMRB) 10.4 Registers TMPM3V6/M3V4 10.4.3 TBxRUN (RUN register) bit symbol After reset bit symbol After reset bit symbol After reset bit symbol TBPRUN TBRUN After reset Bit Symbol Type Function 31-3 − Read as "0". TBPRUN Prescaler operation 0: Stop &...
Page 185 TMPM3V6/M3V4 10.4.4 TBxCR (Control register) bit symbol After reset bit symbol After reset bit symbol After reset bit symbol TBWBF TBSYNC I2TB TRGSEL CSSEL After reset Bit Symbol Type Function 31-8 − Read as "0" TBWBF Double buffer 0: Disable 1: Enable −...
Page 186 16-bit Timer / Event Counters (TMRB) 10.4 Registers TMPM3V6/M3V4 10.4.5 TBxMOD (Mode register) bit symbol After reset bit symbol After reset bit symbol After reset bit symbol TBRSWR TBCP TBCPM TBCLE TBCLK After reset Bit Symbol Type Function 31-7 − Read as "0".
Page 187 TMPM3V6/M3V4 10.4.6 TBxFFCR (Flip-flop control register) bit symbol After reset bit symbol After reset bit symbol After reset bit symbol TBC1T1 TBC0T1 TBE1T1 TBE0T1 TBFF0C After reset Bit Symbol Type Function 31-8 − Read as "0". − Read as "1". TBC1T1 TBxFF0 reverse trigger when the up-counter value is taken into the TBxCP1.
Page 188 16-bit Timer / Event Counters (TMRB) 10.4 Registers TMPM3V6/M3V4 10.4.7 TBxST (Status register) bit symbol After reset bit symbol After reset bit symbol After reset bit symbol INTTBOF INTTB1 INTTB0 After reset Bit Symbol Type Function 31-3 − Read as "0". INTTBOF Overflow flag 0:No overflow occurs...
Page 189 TMPM3V6/M3V4 10.4.8 TBxIM (Interrupt mask register) bit symbol After reset bit symbol After reset bit symbol After reset bit symbol TBIMOF TBIM1 TBIM0 After reset Bit Symbol Type Function 31-3 − Read as "0". TBIMOF Overflow interrupt mask 0:Disable 1:Enable Sets the up-counter overflow interrupt to disable or enable.
Page 190 16-bit Timer / Event Counters (TMRB) 10.4 Registers TMPM3V6/M3V4 10.4.9 TBxUC (Up counter capture register) bit symbol After reset bit symbol After reset bit symbol TBUC After reset bit symbol TBUC After reset Bit Symbol Type Function 31-16 − Read as "0". 15-0 TBUC[15:0] Captures a value by reading up-counter out.
Page 191 TMPM3V6/M3V4 10.4.10 TBxRG0 (Timer register 0) bit symbol After reset bit symbol After reset bit symbol TBRG0 After reset bit symbol TBRG0 After reset Bit Symbol Type Function 31-16 − Read as "0". 15-0 TBRG0[15:0] Sets a value comparing to the up-counter. 10.4.11 TBxRG1 (Timer register 1) bit symbol...
Page 192 16-bit Timer / Event Counters (TMRB) 10.4 Registers TMPM3V6/M3V4 10.4.12 TBxCP0 (Capture register 0) bit symbol After reset bit symbol After reset bit symbol TBCP0 After reset bit symbol TBCP0 After reset Bit Symbol Type Function 31-16 − Read as "0". 15-0 TBCP0[15:0] A value captured from the up-counter is read.
Page 193 TMPM3V6/M3V4 10.5 Description of Operations for Each Circuit The channels operate in the same way, except for the differences in their specifications as shown in Table 10-1. 10.5.1 Prescaler There is a 4-bit prescaler to generate the source clock for up-counter UC. The prescaler input clock φT0 is fs, fperiph/1, fperiph/2, fperiph/4, fperiph/8, fperiph/16 or fperiph/32 selec- ted by CGSYSCR<PRCK[2:0]>...
Page 194 16-bit Timer / Event Counters (TMRB) 10.5 Description of Operations for Each Circuit TMPM3V6/M3V4 Table 10-2 Prescaler Output Clock Resolutions (fc = 40MHz) Select peripheral Select prescaler Prescaler output clock function Select gear clock clock clock CGSYSCR CGSYSCR CGSYSCR φT1 φT4 φT16 <GEAR[2:0]>...
Page 195 TMPM3V6/M3V4 10.5.2 Up-counter (UC) UC is a 16-bit binary counter. ・ Source clock UC source clock, specified by TBxMOD<TBCLK[2:0]>, can be selected from either three types - φT1, φT4 and φT16 - of prescaler output clock or the external clock of the TBxIN pin. ・...
Page 196 16-bit Timer / Event Counters (TMRB) 10.5 Description of Operations for Each Circuit TMPM3V6/M3V4 10.5.4 Capture This is a circuit that controls the timing of latching values from the UC up-counter into the TBxCP0 and TBxCP1 capture registers. The timing with which to latch data is specified by TBxMOD<TBCPM[1:0]>. Software can also be used to import values from the UC up-counter into the capture register;...
Page 197 TMPM3V6/M3V4 10.6 Description of Operations for Each Mode 10.6.1 16-bit interval Timer Mode In the case of generating constant period interrupt, set the interval time to the Timer register (TBxRG0) to generate the INTTBx0 interrupt.Same as TBxRG0, set the interval time to the Timer register (TBxRG1) to gen- erate the INTTBx1 interrupt.
Page 198 16-bit Timer / Event Counters (TMRB) 10.6 Description of Operations for Each Mode TMPM3V6/M3V4 10.6.3 16-bit PPG (Programmable Pulse Generation) Output Mode Square waves with any frequency and any duty (programmable square waves) can be output. The output pulse can be either low-active or high-active Programmable square waves can be output from the TBxOUT pin by triggering the timer flip-flop (TBxFF0) to reverse when the set value of the up-counter (UC) matches the set values of the timer registers (TBxRG0 and TBxRG1).
Page 199 TMPM3V6/M3V4 The block diagram of this mode is shown below. TBxOUT (PPG output) TBxRUN<TBRUN> Selector (TBxFF0) TBxIN 16-bit up-counter φT1 Clear φT4 φT16 Match 16-bit comparator 16-bit comparator Selector Selector TBxRG0 TBxRG1 Write Write TBxRG0 TBxRG1 Register buffer0 Register buffer1 TBxCR<TBWBF>...
Page 200 16-bit Timer / Event Counters (TMRB) 10.6 Description of Operations for Each Mode TMPM3V6/M3V4 10.6.4 External Trigger PPG (Programmable Square Wave) Output Mode An external trigger count start mode provides one-shot pulse output with a short delay. 1. Set the 16-bit up-counter to count-up on the rising edge of TBxIN pin (TBxCR<TRGSEL, CSSEL>= "01") while the up-counter (UC) is stopping (TBxRUN<TBRUN>...
Page 201 TMPM3V6/M3V4 10.6.5 Timer synchronous mode This mode enables the timers to start synchronously. If the mode is used with PPG output, the output can be applied to drive a motor. TMRB is consisted of pairs of 4-channel TMRB. If one channel starts, remaining 3 channels can be start syn- chronously.
Page 202 16-bit Timer / Event Counters (TMRB) 10.7 Applications using the Capture Function TMPM3V6/M3V4 10.7 Applications using the Capture Function The capture function can be used to develop many applications, including those described below: 1. One-shot pulse output triggered by an external pulse 2.
Page 203 TMPM3V6/M3V4 The followings show the settings in the case that 2 ms width one-shot pulse is output after 3ms by trigger- ing TBxIN input at the rising edge. (φT1 is selected for counting.) [Main processing] Capture setting by TBxIN0 Set PORT registers. Allocates corresponding port to TBxIN.
Page 204 16-bit Timer / Event Counters (TMRB) 10.7 Applications using the Capture Function TMPM3V6/M3V4 10.7.2 Frequency measurement The frequency of an external clock can be measured by using the capture function. To measure frequency, another 16-bit timer is used in combination with the 16-bit event counter mode. As an example, we explain with TMRB0 and TMRB7.
Page 205 TMPM3V6/M3V4 The "Low" level width of an external pulse can also be measured. In such cases, the difference between C2 generated the first time and C1 generated the second time is initially obtained by performing the second stage of INTCAPx0 interrupt processing as shown in "Figure 10-9 Pulse Width Measurement" and this differ- ence is multiplied by the cycle of the prescaler output clock to obtain the "Low"...
Page 206 16-bit Timer / Event Counters (TMRB) 10.7 Applications using the Capture Function TMPM3V6/M3V4 Page 184 2019-02-06...
Page 207 TMPM3V6/M3V4 11. Universal Asynchronous Receiver-Transmitter Circuit (UART) 11.1 Outline The universal asynchronous receiver-transmitter circuit provides the following features: ・ Transmit/receive data format Data length: selectable from 5, 6, 7, or 8 bits With/without a parity bit STOP bit length: selectable from 1 bit or 2 bits ・...
Page 208 Universal Asynchronous Receiver-Transmitter Circuit (UART) 11.2 Structure TMPM3V6/M3V4 11.2 Structure Figure 11-1 shows a block diagram of UART. Read data[11:0] Write data[7:0] 12bit x 32 8bit x 32 receive transmit FIFO FIFO TXD[7:0] RXD[11:0] interface register block Control and status UTxTXD Transmitter Baud16...
Page 209 TMPM3V6/M3V4 11.3 Registers 11.3.1 List of Registers The following table lists the control registers and their addresses. For base addresses, refer to "A list of peripheral function base addresses" in the chapter on "Memory Map." Register name Address (Base+) Data register UARTxDR 0x0000 Receive status register...
Page 210 Universal Asynchronous Receiver-Transmitter Circuit (UART) 11.3 Registers TMPM3V6/M3V4 11.3.2 UARTxDR (Data Register) Bit symbol After reset Bit symbol After reset Bit symbol After reset Bit symbol DATA After reset Bit symbol Type Function 31-12 − Read as "0". Overrun error 0: No error 1: Error If the FIFO has been full when receiving data, this bit is set to "1".
Page 211 TMPM3V6/M3V4 11.3.3 UARTxRSR (Receive Status Register) Both UARTxRSR and UARTxECR registers are mapped on the same address. Bit symbol After reset Bit symbol After reset Bit symbol After reset Bit symbol After reset Bit symbol Type Function 31-4 − Read as "0". Overrun error 0: No error 1: Error...
Page 212 Universal Asynchronous Receiver-Transmitter Circuit (UART) 11.3 Registers TMPM3V6/M3V4 11.3.4 UARTxECR (Error Clear Register) Bit symbol After reset Bit symbol After reset Bit symbol After reset Bit symbol After reset Bit symbol Type Function 31-4 − Read as "0". When data is written to UARTxECR, each framing, parity, break, and overrun errors are cleared. This clear- ing is executed regard less of the data value.
Page 213 TMPM3V6/M3V4 11.3.5 UARTxFR (UART Flag Register) Bit symbol After reset Bit symbol After reset Bit symbol After reset Bit symbol TXFE RXFF TXFF RXFE BUSY After reset Bit symbol Type Function 31-9 − Read as an undefined value. Read as an undefined value. TXFE When UARTxLCR_H<FEN>...
Page 214 Universal Asynchronous Receiver-Transmitter Circuit (UART) 11.3 Registers TMPM3V6/M3V4 11.3.6 UARTxIBRD (UART Integer Baud-rate Register) Bit symbol After reset Bit symbol After reset Bit symbol BAUDDIVINT After reset Bit symbol BAUDDIVINT After reset Bit symbol Type Function 31-16 − Read as an undefined value. 15-0 BAUDDIVINT Integer baud-rate divisor (0x0002 to 0xFFFF)
Page 215 TMPM3V6/M3V4 11.3.7 UARTxFBRD (UART Fractional Baud-rate Register) Bit symbol After reset Bit symbol After reset Bit symbol After reset Bit symbol BAUDDIVFRAC After reset Bit symbol Type Function 31-6 − Read as "0". 5 -0 BAUD Fractional baud-rate divisor (0x01 to 0x3F) DIVFRAC The fractional part of a baud-rate divisor value.
Page 216 Universal Asynchronous Receiver-Transmitter Circuit (UART) 11.3 Registers TMPM3V6/M3V4 11.3.8 UARTxLCR_H (UART Line Control Register) Bit symbol After reset Bit symbol After reset Bit symbol After reset Bit symbol WLEN STP2 After reset Bit symbol Type Function 31-8 − Read as "0". Selects a stick parity 0: A stick parity is disabled.
Page 217 TMPM3V6/M3V4 Table 11-1 Truth table of UARTxLCR_H <SPS>, <EPS> and <PEN> Even parity se- Parity Stick parity se- lection Parity selection (Transmission or check) lection <SPS> enable <PEN> <EPS> × × No transmission and check Even parity transmission or even parity re- ception Odd parity transmission or odd parity re- ception...
Page 218 Universal Asynchronous Receiver-Transmitter Circuit (UART) 11.3 Registers TMPM3V6/M3V4 11.3.9 UARTxCR (UART Control Register) Bit symbol After reset Bit symbol After reset Bit symbol After reset Bit symbol UARTEN After reset Bit symbol Type Function 31-16 − Read as an undefined value. Write as "0".
Page 219 TMPM3V6/M3V4 11.3.10 UARTxIFLS (UART Interrupt FIFO Level Selection Register) Bit symbol After reset Bit symbol After reset Bit symbol After reset Bit symbol RXIFLSEL TXIFLSEL After reset Bit symbol Type Function 31-6 − Read as an undefined value. RXIFLSEL[2:0] Selects the reception interrupt FIFO level 000: The Receive FIFO ≥...
Page 220 Universal Asynchronous Receiver-Transmitter Circuit (UART) 11.3 Registers TMPM3V6/M3V4 11.3.11 UARTxIMSC (UART Interrupt Disable/Enable Register) Bit symbol After reset Bit symbol After reset Bit symbol OEIM BEIM PEIM After reset Bit symbol FEIM RTIM TXIM RXIM After reset Bit symbol Type Function 31-11 −...
Page 221 TMPM3V6/M3V4 11.3.12 UARTxRIS (UART Raw Interrupt Status Register) Bit symbol After reset Bit symbol After reset Bit symbol OERIS BERIS PERIS After reset Bit symbol FERIS RTRIS TXRIS RXRIS After reset Undefined Undefined Undefined Undefined Bit symbol Type Function 31-11 −...
Page 222 Universal Asynchronous Receiver-Transmitter Circuit (UART) 11.3 Registers TMPM3V6/M3V4 11.3.13 UARTxMIS (UART Masked Interrupt Status Register) Bit symbol After reset Bit symbol After reset Bit symbol OEMIS BEMIS PEMIS After reset Bit symbol FEMIS RTMIS TXMIS RXMIS After reset Undefined Undefined Undefined Undefined Bit symbol...
Page 223 TMPM3V6/M3V4 11.3.14 UARTxICR (UART Interrupt Clear Register) Bit symbol After reset Bit symbol After reset Bit symbol OEIC BEIC PEIC After reset Bit symbol FEIC RTIC TXIC RXIC After reset Bit symbol Type Function 31-11 − Write as "0". OEIC Overrun error interrupt clear 0: Invalid 1: Clear...
Page 224 Universal Asynchronous Receiver-Transmitter Circuit (UART) 11.3 Registers TMPM3V6/M3V4 11.3.15 UARTxHCCR (50% Duty Control Register) Bit symbol After reset Bit symbol After reset Bit symbol After reset Bit symbol HCLPB HCZR HCST HCMD HCCR After reset Bit symbol Type Function 31-8 −...
Page 225 TMPM3V6/M3V4 11.4 Operation Description 11.4.1 Transmit FIFO and Receive FIFO 11.4.1.1 Transmit FIFO The transmit FIFO is an 8-bit width and 32-deep memory buffer. The CPU data written via APB inter- face is stacked to this FIFO until the data is read by the transmit. When the transmit FIFO is disabled, it can be served as a 1-byte hold register.
Page 226 Universal Asynchronous Receiver-Transmitter Circuit (UART) 11.4 Operation Description TMPM3V6/M3V4 11.4.3 Baud-rate Generator The baud-rate generator outputs internal clocks: Baud16 and IrLPBaud16. Baud16 generates the timing for UART transmission/reception control. IrLPBaud16 generates a pulse width of IrDA encode transmit bit stream in the low power mode. The baud-rate is calculated by the following equation using the f input from the UART and a baud- UARTCLK...
Page 227 TMPM3V6/M3V4 11.4.6 Interrupt Generation Logic The UART outputs a maskable interrupt according to interrupt events. 11.4.6.1 UART Interrupt Generation Circuit Interrupt request flag generation circuit 1. Generation circuit for break, parity and framing error flags An interrupt request flag changes in real-time associated with F/F. Each flag is cleared when data is written to the corresponding interrupt clear register.
Page 228 Universal Asynchronous Receiver-Transmitter Circuit (UART) 11.4 Operation Description TMPM3V6/M3V4 UARTxMIS<OEMIS> UARTxRIS<OERIS> UARTxIMSC<OEIM> (Enable signal) UARTxMIS<BEMIS> UARTxRIS<BERIS> UARTxIMSC<BEIM> (Enable signal) UARTxMIS<PEMIS> UARTxRIS<PERIS> UARTxIMSC<PEIM> (Enable signal) UARTxMIS<FEMIS> UARTxRIS<FERIS> UARTxIMSC<FEIM> (Enable signal) UARTxMIS<RTMIS> UARTxRIS<RTRIS> UARTxIMSC<RTIM> (Enable signal) INTUARTx UARTxMIS<TXMIS> UARTxRIS<TXRIS> UARTxIMSC<TXIM> (Enable signal) UARTxMIS<RXMIS>...
Page 229 TMPM3V6/M3V4 11.4.7 50% Duty Mode 11.4.7.1 Outline The following functions are available in the 50% duty mode. ・ Communication pins: For transmission UTxTXD50A and UTxTXD50B For reception UTxRXD50 ・ 1-pin transmission mode ・ 2-pin transmission mode ・ Selection of the start bit pin ・...
Page 230 Universal Asynchronous Receiver-Transmitter Circuit (UART) 11.4 Operation Description TMPM3V6/M3V4 2-pin transmission mode When "1" is set to UARTxHCCR<HCMD>, 2-pin transmission mode is enabled. Data "0" is trans- mitted through UTxTXD50A and UTxTXD50B alternatively. Data bit Parity Stop Start UTxTXD UTxTXD50A 50% duty 50% duty UTxTXD50B...
Page 231 TMPM3V6/M3V4 Detection control of data "0" in the reception period The detection width can be set with UARTxHCCR<HCZR[2:0]>. The width is one that the data is recognized as "0" against width of one bit in 100% duty. After a falling edge of data of "0" is detected, if "0" level continues over than the specified detec- tion width, the data is captured as data of "0".
Page 232 Universal Asynchronous Receiver-Transmitter Circuit (UART) 11.4 Operation Description TMPM3V6/M3V4 Page 210 2019-02-06...
Page 233 TMPM3V6/M3V4 12. Serial Channel with 4bytes FIFO (SIO/UART) 12.1 Overview Serial channel (SIO/UART) has the modes shown below. ・ Synchronous communication mode (I/O interface mode) ・ Asynchronous communication mode (UART mode) Their features are given in the following. ・ Transfer Clock Dividing by the prescaler, from the peripheral clock (φT0) frequency into 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128.
Page 234 Serial Channel with 4bytes FIFO (SIO/UART) 12.2 Configuration TMPM3V6/M3V4 12.2 Configuration Serial channel block diagram and serial clock generator circuit diagram are shown in belows: SIOCLK For I/O interface mode SCLKx Output Interrupt request (INTRXx) Interrupt request (INTTXx) Serial channel SCxMOD0 Receive counter Transmit counter...
Page 235 TMPM3V6/M3V4 12.3 Registers Description 12.3.1 Registers List The table below shows control registers and their addresses. For detail of the base address, refer to "Address lists of peripheral functions" of "Memory Map" chapter. Register name Address (Base+) Enable register SCxEN 0x0000 Buffer register SCxBUF...
Page 236 Serial Channel with 4bytes FIFO (SIO/UART) 12.3 Registers Description TMPM3V6/M3V4 12.3.2 SCxEN (Enable Register) bit symbol After reset bit symbol After reset bit symbol After reset bit symbol BRCKSEL SIOE After reset Bit Symbol Type Function 31-2 − Read as "0". BRCKSEL Selects input clock for prescaler.
Page 237 TMPM3V6/M3V4 12.3.3 SCxBUF (Buffer Register) SCxBUF works as a transmit buffer or FIFO for write operation and as a receive buffer or FIFO for read op- eration. bit symbol After reset bit symbol After reset bit symbol After reset bit symbol TB / RB After reset Bit Symbol...
Page 238 Serial Channel with 4bytes FIFO (SIO/UART) 12.3 Registers Description TMPM3V6/M3V4 12.3.4 SCxCR (Control Register) bit symbol After reset bit symbol After reset bit symbol EHOLD TXDEMP TIDLE After reset bit symbol EVEN OERR PERR FERR SCLKS After reset Bit Symbol Type Function 31-15...
Page 239 TMPM3V6/M3V4 Bit Symbol Type Function SCLKS Selecting input clock edge (For I/O Interface mode) Set to "0" in the clock output mode. 0: Data in the transmit buffer is sent to TXDx pin every one bit on the falling edge of RXDx pin. Data from RXDx pin is received in the receive buffer every one bit on the rising edge of RXDx pin.
Page 240 Serial Channel with 4bytes FIFO (SIO/UART) 12.3 Registers Description TMPM3V6/M3V4 12.3.5 SCxMOD0 (Mode Control Register 0) bit symbol After reset bit symbol After reset bit symbol After reset bit symbol CTSE After reset Bit Symbol Type Function 31-8 − Read as "0". Transmit data bit 8 (For only UART mode) Writes the 9th bit of transmit data in the 9-bit UART mode.
Page 241 TMPM3V6/M3V4 12.3.6 SCxMOD1 (Mode Control Register 1) bit symbol After reset bit symbol After reset bit symbol After reset bit symbol I2SC FDPX SINT After reset Bit Symbol Type Function 31-8 − Read as "0". I2SC IDLE 0: Stop 1: Operate Specifies operation in the IDLE mode.
Page 242 Serial Channel with 4bytes FIFO (SIO/UART) 12.3 Registers Description TMPM3V6/M3V4 12.3.7 SCxMOD2 (Mode Control Register 2) bit symbol After reset bit symbol After reset bit symbol After reset bit symbol TBEMP RBFLL TXRUN SBLEN DRCHG WBUF SWRST After reset Bit Symbol Type Function 31-8...
Page 243 TMPM3V6/M3V4 Bit Symbol Type Function SWRST[1:0] Software reset Overwriting "01" in place of "10" generates a software reset. When a software reset is executed, the following bits are initialized and the transmit/receive circuit and FIFO become initial state (Note1)(Note2). Register SCxMOD0 <RXE>...
Page 244 Serial Channel with 4bytes FIFO (SIO/UART) 12.3 Registers Description TMPM3V6/M3V4 12.3.8 SCxBRCR (Baud Rate Generator Control Register) bit symbol After reset bit symbol After reset bit symbol After reset bit symbol BRADDE BRCK After reset Bit Symbol Type Function 31-8 −...
Page 245 TMPM3V6/M3V4 12.3.9 SCxBRADD (Baud Rate Generator Control Register 2) bit symbol After reset bit symbol After reset bit symbol After reset bit symbol After reset Bit Symbol Type Function 31-4 − Read as "0". BRK[3:0] Specify K for the "N + (16 − K)/16" division (For UART mode) 0000: Prohibited 0001: K = 1 0010: K = 2...
Page 246 Serial Channel with 4bytes FIFO (SIO/UART) 12.3 Registers Description TMPM3V6/M3V4 12.3.10 SCxFCNF (FIFO Configuration Register) bit symbol After reset bit symbol After reset bit symbol After reset bit symbol RFST TFIE RFIE RXTXCNT CNFG After reset Bit Symbol Type Function 31-8 −...
Page 247 TMPM3V6/M3V4 Note 1: Regarding Transmit FIFO, the maximum number of bytes being configured is always available. (See also <CNFG>.) Note 2: The FIFO can not be used in 9 bit UART mode. Page 225 2019-02-06...
Page 248 Serial Channel with 4bytes FIFO (SIO/UART) 12.3 Registers Description TMPM3V6/M3V4 12.3.11 SCxRFC (Receive FIFO Configuration Register) bit symbol After reset bit symbol After reset bit symbol After reset bit symbol RFCS RFIS After reset Bit Symbol Type Function 31-8 − Read as "0".
Page 249 TMPM3V6/M3V4 12.3.12 SCxTFC (Transmit FIFO Configuration Register) bit symbol After reset bit symbol After reset bit symbol TBCLR After reset bit symbol TFCS TFIS After reset Bit Symbol Type Function 31-9 − Read as "0". TBCLR Transmit buffer clear 0: Don’t care 1: Clear When SCxTFC<TBCLR>...
Page 250 Serial Channel with 4bytes FIFO (SIO/UART) 12.3 Registers Description TMPM3V6/M3V4 12.3.13 SCxRST (Receive FIFO Status Register) bit symbol After reset bit symbol After reset bit symbol After reset bit symbol RLVL After reset Bit Symbol Type Function 31-8 − Read as "0". Receive FIFO Overrun.
Page 251 TMPM3V6/M3V4 12.3.14 SCxTST (Transmit FIFO Status Register) bit symbol After reset bit symbol After reset bit symbol After reset bit symbol TLVL After reset Bit Symbol Type Function 31-8 − Read as "0". Transmit FIFO Under run. (Note) 0: Not generated 1: Generated −...
Page 252 Serial Channel with 4bytes FIFO (SIO/UART) 12.4 Operation in Each Mode TMPM3V6/M3V4 12.4 Operation in Each Mode Table 12-2 shows the modes. Table 12-2 Modes Specifies Mode type Data length Transfer direction whether to use STOP bit length (transmit) parity bits. Synchronous communication mode Mode 0...
Page 253 TMPM3V6/M3V4 12.5 Data Format 12.5.1 Data Format List Figure 12-3 shows data format. Mode0 (I/O interface mode) / LSB first ● bit 0 Transmission direction Mode0 (I/O interface mode ) / MSB first ● bit 7 Transmission direction Mode1 (7bits UART mode) ●...
Page 254 Serial Channel with 4bytes FIFO (SIO/UART) 12.5 Data Format TMPM3V6/M3V4 12.5.2 Parity Control The parity bit can be added with a transmitted data only in the 7- or 8-bit UART mode. And the received par- ity bit can be compared with a generated one. Setting "1"...
Page 255 TMPM3V6/M3V4 12.6 Clock Control 12.6.1 Prescaler There is a 7-bit prescaler to divide a prescaler input clock φT0 by 1, 2, 4, 8, 16, 32, 64 and 128. Use the CGSYSCR and SCxEN<BRCKSEL> in the clock/mode control block to select the input clock of the prescaler.
Page 256 Serial Channel with 4bytes FIFO (SIO/UART) 12.6 Clock Control TMPM3V6/M3V4 Divide Function Setting Divide by N Divide by K Mode SCxBRCR<BRADDE> SCxBRCR<BRS[3:0]> SCxBRADD<BRK[3:0]> I/O interface Divide by N 1 to 16 (Note) Divide by N 1 to 16 UART N + (16-K)/16 division 2 to 15 1 to 15 Note: 1/N (N=1) frequency division ratio can be used only when a double buffer is enabled.
Page 257 TMPM3V6/M3V4 12.6.2.2 Clock Selection Circuit A clock can be selected by setting the modes and the register. Modes can be specified by setting the SCxMOD0<SM[1:0]> The clock in I/O interface mode is selected by setting SCxCR<IOC><SCLKS>. The clock in UART mode is selected by setting SCxMOD0<SC[1:0]>. Transfer Clock in I/O interface mode Table 12-3 shows clock selection in I/O interface mode.
Page 258 Serial Channel with 4bytes FIFO (SIO/UART) 12.6 Clock Control TMPM3V6/M3V4 Transfer clock in the UART mode Table 12-4 shows the clock selection in the UART mode. In the UART mode, selected clock is divi- ded by 16 in the receive counter or the transmit counter before use. Table 12-4 Clock Selection in UART Mode Mode Clock selection...
Page 259 TMPM3V6/M3V4 12.6.3 Transmit/Receive Buffer and FIFO 12.6.3.1 Configuration Figure 12-4 shows the configuration of transmit buffer, receive buffer and FIFO. Appropriate settings are required for using buffer and FIFO. The configuration may be predefined depend- ing on the mode. RXDx TXDx Receive shift register Transmit shift register...
Page 260 Serial Channel with 4bytes FIFO (SIO/UART) 12.6 Clock Control TMPM3V6/M3V4 12.6.3.3 Initialize Transmit Buffer When transmission is stopped with a data in the transmit buffer, it is necessary to initialize the transmit buffer before new transmit data is written to transmit buffer. The transmit buffer must be initialized when the transmit operation is stopped.
Page 261 TMPM3V6/M3V4 12.7 Status Flag The SCxMOD2 has two types of flag. This bit is significant only when the double buffer is enabled. <RBFLL> is a flag to show that the receive buffer is full. When one frame of data is received and the data is moved from the receive shift register to the receive buffers, this bit changes to "1".
Page 262 Serial Channel with 4bytes FIFO (SIO/UART) 12.8 Error Flag TMPM3V6/M3V4 12.8.2 PERR Flag This flag indicates a parity error in the UART mode and an under-run error or completion of transmit in the I/O interface mode. In the UART mode, <PERR> is set to "1" when the parity generated from the received data is different from the received parity bit.
Page 263 TMPM3V6/M3V4 12.9 Receive 12.9.1 Receive Counter The receive counter is a 4-bit binary counter and is up-counted by SIOCLK. In the UART mode, sixteen SIOCLK clock pulses are used in receiving a single data bit and the data sym- bol is sampled at the eighth pulse. 12.9.2 Receive Control Unit 12.9.2.1...
Page 264 Serial Channel with 4bytes FIFO (SIO/UART) 12.9 Receive TMPM3V6/M3V4 12.9.3.2 Receive FIFO Operation When FIFO is enabled, the received data is moved from receive buffer to receive FIFO and the receive buffer full flag is cleared immediately. An interrupt will be generated according to the SCxRFC<RIL[1:0] >.
Page 265 TMPM3V6/M3V4 12.9.3.3 I/O interface mode with clock output mode In the I/O interface mode with clock output mode setting, clock stops when all received data is stored in the receive buffer and FIFO. So, in this mode, the over-run error flag has no meaning. The timing of SCLK output stop and re-output depends on receive buffer and FIFO.
Page 266 Serial Channel with 4bytes FIFO (SIO/UART) 12.9 Receive TMPM3V6/M3V4 12.9.3.4 Read Received Data In spite of enabling or disabling FIFO, read the received data from the receive buffer (SCxBUF). When receive FIFO is disabled, the buffer full flag SCxMOD2<RBFLL> is cleared to "0" by this read- ing.
Page 267 TMPM3V6/M3V4 12.10 Transmit 12.10.1 Transmit Counter The transmit counter is a 4-bit binary counter and is counted by SIOCLK as in the case of the receive coun- ter. In UART mode, it generates a transmit clock (TXDCLK) on every 16th clock pulse. SIOCLK 15 16 10 11 12 13 14 15 16...
Page 268 Serial Channel with 4bytes FIFO (SIO/UART) 12.10 Transmit TMPM3V6/M3V4 12.10.3 Transmit Operation 12.10.3.1 Operation of Transmit Buffer If double buffering is disabled, the CPU writes data only to transmit shift register and the transmit inter- rupt INTTXx is generated upon completion of data transmission. If double buffering is enabled (including the case the transmit FIFO is enabled), data written to the trans- mit buffer is moved to the transmit shift register.
Page 269 TMPM3V6/M3V4 12.10.3.2 Transmit FIFO Operation When FIFO is enabled, the maximum 5-byte data can be stored using the transmit buffer and FIFO. Once transmission is enabled, data is transferred to the transmit shift register from the transmit buffer and start transmission. If data exists in the FIFO, the data is moved to the transmit buffer immediately, and the <TBEMP>...
Page 270 Serial Channel with 4bytes FIFO (SIO/UART) 12.10 Transmit TMPM3V6/M3V4 12.10.3.3 Transmit in I/O interface Mode with Clock Output Mode In the I/O interface mode with clock output mode, the clock output automatically stops when all data trans- mission is completed and underrun error will not occur. The timing of suspension and resume of clock output is different depending on the buffer and FIFO us- age.
Page 271 TMPM3V6/M3V4 12.10.3.5 Under-run error In the I/O interface mode with clock input mode and if FIFO is empty and if no data is set in transmit buf- fer before the next frame clock input, which occurs upon completion of data transmission from transmit shift register, an under-run error occurs and SCxCR<PERR>...
Page 272 Serial Channel with 4bytes FIFO (SIO/UART) 12.11 Handshake function TMPM3V6/M3V4 12.11 Handshake function The function of the handshake is to enable frame-by-frame data transmission by using the CTSx (Clear to send) pin and to prevent over-run errors. This function can be enabled or disabled by SCxMOD0<CTSE>. When the CTSx pin is set to "High"...
Page 273 TMPM3V6/M3V4 12.12 Interrupt/Error Generation Timing 12.12.1 Receive Interrupts Figure 12-13 shows the data flow of receive operation and the route of read. RXDx Receive shift register (1)Reading in the single buffer configuration : If the receive buffer is empty, An interrupt is generated after receiving all bits. the data is moved.
Page 274 Serial Channel with 4bytes FIFO (SIO/UART) 12.12 Interrupt/Error Generation Timing TMPM3V6/M3V4 12.12.2 Transmit interrupts Figure 12-14 shows the data flow of transmit operation and the route of read. TXDx Transmit shift register (1)Writing in the single buffer configuration : If the shift register is empty, An interrupt is generated after transmitting all bits.
Page 275 TMPM3V6/M3V4 12.12.2.2 FIFO When the FIFO is used, a transmit interrupt occurs depending on the timing described in Table 12-10 and the condition specified with SCxTFC<TFIS>. Table 12-10 Transmit Interrupt conditions in use of FIFO SCxTFC<TFIS> Interrupt condition Interrupt generation timing ・When transmitted data is transferred from transmit FIFO to transmit buffer When FIFO fill level (SCxTST<TLVL[2:0]>) = Transmit "0"...
Page 276 Serial Channel with 4bytes FIFO (SIO/UART) 12.13 Software Reset TMPM3V6/M3V4 12.13 Software Reset Software reset is generated by writing SCxMOD2<SWRST[1:0]> as "10" followed by "01". As a result, SCxMOD0<RXE>, SCxMOD1<TXE>, SCxMOD2<TBEMP><RBFLL><TXRUN>, SCxCR <OERR><PERR><FERR> are initialized. And the receive circuit and the transmit circuit become initial state. Other states are maintained.
Page 277 TMPM3V6/M3V4 12.14 Operation in Each Mode 12.14.1 Mode 0 (I/O interface mode) The I/O interface mode is selected by setting SCxMOD0<SM[1:0]> to "00". Mode 0 consists of two modes, the clock output mode to output synchronous clock (SCLK) and the clock in- put mode to accept synchronous clock (SCLK) from an external source.
Page 278 Serial Channel with 4bytes FIFO (SIO/UART) 12.14 Operation in Each Mode TMPM3V6/M3V4 Transmit data write timing SCLKx output TXDx bit 7 bit 0 bit 0 bit 1 bit 6 INTTXx interrupt request <WBUF> = "0" (if double buffering is disabled) (SCxCR<TIDLE>="10") Transmit data write timing SCLKx output...
Page 279 TMPM3V6/M3V4 Clock Input Mode ・ If double buffering is disabled (SCxMOD2<WBUF> = "0") If the clock is input in the condition where data is written in the transmit buffer, 8-bit da- ta is output from the TXDx pin. When all data is output, an interrupt INTTXx is gener- ated.
Page 280 Serial Channel with 4bytes FIFO (SIO/UART) 12.14 Operation in Each Mode TMPM3V6/M3V4 Transmit data write timing SCLKx input (SCxCR<SCLKS>=0 Rising edge mode) SCLKx input (SCxCR<SCLKS>=1 Falling edge mode) bit 0 bit 0 bit 1 bit 5 bit 6 bit 7 bit 1 TXDx INTTXx interrupt request...
Page 281 TMPM3V6/M3V4 12.14.1.2 Receive Clock Output Mode The clock output starts by setting the receive enable bit SCxMOD0<RXE> to "1". ・ If double buffer is disabled (SCxMOD2<WBUF> = "0") A clock is output from the SCLKx pin and the next data is stored into the shift register each time the CPU reads received data.
Page 282 Serial Channel with 4bytes FIFO (SIO/UART) 12.14 Operation in Each Mode TMPM3V6/M3V4 Receive data read timing SCLKx output RXDx bit 0 bit 1 bit 6 bit 7 bit 0 INTRXx interrupt request <WBUF> = "0" (if double buffering is disabled) Receive data read timing SCLKx output...
Page 283 TMPM3V6/M3V4 clock input mode In the clock input mode, receiving double buffering is always enabled, the received data can be moved to the receive buffer from the shift register, and the receive buffer can receive the next data suc- cessively. The INTRXx receive interrupt is generated each time received data is moved to the receive buffer.
Page 284 Serial Channel with 4bytes FIFO (SIO/UART) 12.14 Operation in Each Mode TMPM3V6/M3V4 12.14.1.3 Transmit and Receive (Full-duplex) Clock Output Mode ・ If double buffers are disabled (SCxMOD2<WBUF> = "0") Clock is output when the CPU writes data to the transmit buffer. Subsequently, a data is shifted into receive buffer and the INTRXx is generated.
Page 285 TMPM3V6/M3V4 Receive data read timing Transmit data write timing SCLKx output TXDx bit 0 bit 0 bit 1 bit 5 bit 6 bit 7 bit 1 RXDx bit 0 bit 0 bit 1 bit 5 bit 6 bit 7 bit 1 INTTXx interrupt request INTRXx interrupt request <WBUF>...
Page 286 Serial Channel with 4bytes FIFO (SIO/UART) 12.14 Operation in Each Mode TMPM3V6/M3V4 Clock Input Mode ・ If double buffers are disabled. (SCxMOD2<WBUF> = "0") When receiving data, double buffer is always enabled regardless of the SCxMOD2 <WBUF> settings. A data written in the transmit buffer is outputted from the TXDx pin and a data is shif- ted into the receive buffer when the clock input becomes active.
Page 287 TMPM3V6/M3V4 Receive data read timing Transmit data write timing SCLKx input (SCxCR<SCLKS>=”0” Rising mode) SCLKx input (SCxCR<SCLKS>=”1” Falling mode) bit 0 bit 0 bit 1 bit 5 bit 6 bit 7 bit 1 TXDx bit 0 bit 0 bit 1 bit 5 bit 6 bit 7...
Page 288 Serial Channel with 4bytes FIFO (SIO/UART) 12.14 Operation in Each Mode TMPM3V6/M3V4 12.14.2 Mode 1 (7-bit UART mode) The 7-bit UART mode is selected by setting SCxMOD0<SM[1:0]> to "01". In this mode, parity bits can be added to the transmit data stream; SCxCR<PE> controls the parity enable/dis- able setting.
Page 289 TMPM3V6/M3V4 SCxMOD0 ← Set 8-bit UART mode SCxCR ← Odd parity enabled SCxBRCR ← Set 9600bps SCxMOD0 ← Reception enabled x: don’t care - : no change 12.14.4 Mode 3 (9-bit UART mode) The 9-bit UART mode is selected by setting SCxMOD0<SM[1:0]> to "11". In this mode, parity bits must be disabled (SCxCR<PE>...
Page 290 Serial Channel with 4bytes FIFO (SIO/UART) 12.14 Operation in Each Mode TMPM3V6/M3V4 12.14.4.2 Protocol 1. Select the 9-bit UART mode for the master and slave controllers. 2. Set SCxMOD0<WU> to "1" for the slave controllers to make them ready to receive data. 3.
Page 291 TMPM3V6/M3V4 13. Serial Bus Interface (I2C/SIO) The TMPM3V6/M3V4 contains 1 Serial Bus Interface (I2C/SIO) channel, in which the following two operating modes are included: ・ I2C bus mode (with multi-master capability) ・ Clock-synchronous 8-bit SIO mode In the I2C bus mode, the I2C/SIO is connected to external devices via SCL and SDA. In the clock-synchronous 8-bit SIO mode, the I2C/SIO is connected to external devices via SCK, SI and SO.
Page 292 Serial Bus Interface (I2C/SIO) 13.1 Configuration TMPM3V6/M3V4 13.1 Configuration The configuration is shown in Figure 13-1. INTSBI interrupt request clock Input/ control Output control Frequency fsys Divider data control Transfer I2C bus control clock circuit synchroni- Noise I2C bus zation canceller Shift Noise...
Page 293 TMPM3V6/M3V4 13.2 Register The following registers control the serial bus interface and provide its status information for monitoring. The register below performs different functions depending on the mode. For details, refer to "13.4 Control Reg- isters in the I2C Bus Mode" and "13.7 Control register of SIO mode". 13.2.1 Registers for each channel The tables below show the registers and register addresses for each channel.
Page 294 Serial Bus Interface (I2C/SIO) 13.3 I2C Bus Mode Data Format TMPM3V6/M3V4 13.3 I2C Bus Mode Data Format Figure 13-2 shows the data formats used in the I2C bus mode. (a) Addressing format 8 bit 1 to 8 bits 1 to 8 bits Data Data Slave address...
Page 295 TMPM3V6/M3V4 13.4 Control Registers in the I2C Bus Mode The following registers control the serial bus interface in the I2C bus mode and provide its status information for monitoring. 13.4.1 SBICR0(Control register 0) bit symbol After reset bit symbol After reset bit symbol After reset bit symbol...
Page 296 Serial Bus Interface (I2C/SIO) 13.4 Control Registers in the I2C Bus Mode TMPM3V6/M3V4 13.4.2 SBICR1(Control register 1) bit symbol After reset bit symbol After reset bit symbol After reset SCK0 / bit symbol SCK2 SCK1 SWRMON After reset 1(Note3) Bit Symbol Type Function 31-8...
Page 297 TMPM3V6/M3V4 Note 1: Clear <BC[2:0]> to "000" before switching the operation mode to the SIO mode. Note 2: For details on the SCL line clock frequency, refer to "13.5.1 Serial Clock". Note 3: After a reset, the <SCK[0]/SWRMON> bit is read as "1". However, if the SIO mode is selected at the SBICR2 register, the initial value of the <SCK[0]>...
Page 298 Serial Bus Interface (I2C/SIO) 13.4 Control Registers in the I2C Bus Mode TMPM3V6/M3V4 13.4.3 SBICR2(Control register 2) This register serves as SBISR register by reading it. bit symbol After reset bit symbol After reset bit symbol After reset bit symbol SBIM SWRST After reset...
Page 299 TMPM3V6/M3V4 13.4.4 SBISR (Status Register) This register serves as SBICR2 by writing to it. bit symbol After reset bit symbol After reset bit symbol After reset bit symbol After reset Bit Symbol Type Function 31-8 Read as 0. Master/slave selection monitor 0: Slave mode 1: Master mode Transmit/receive selection monitor...
Page 300 Serial Bus Interface (I2C/SIO) 13.4 Control Registers in the I2C Bus Mode TMPM3V6/M3V4 13.4.5 SBIBR0(Serial bus interface baud rate register 0) bit symbol After reset bit symbol After reset bit symbol After reset bit symbol I2SBI After reset Bit Symbol Type Function 31-8...
Page 301 TMPM3V6/M3V4 13.4.7 SBII2CAR (I2Cbus address register) bit symbol After reset bit symbol After reset bit symbol After reset bit symbol After reset Bit Symbol Type Function 31-8 Read as 0. SA[6:0] Set the slave address when the SBI acts as a slave device. Specify address recognition mode.
Page 302 Serial Bus Interface (I2C/SIO) 13.5 Control in the I2C Bus Mode TMPM3V6/M3V4 13.5 Control in the I2C Bus Mode 13.5.1 Serial Clock 13.5.1.1 Clock source SBICR1<SCK[2:0]> specifies the maximum frequency of the serial clock to be output from the SCL pin in the master mode.
Page 303 TMPM3V6/M3V4 Master A completes counting of its "Low" level period at the point b, and brings its internal SCL out- put to the "High" level. However, Master B still keeps the SCL bus line at the "Low" level, and Master A stops counting of its "High"...
Page 304 Serial Bus Interface (I2C/SIO) 13.5 Control in the I2C Bus Mode TMPM3V6/M3V4 13.5.6 Configuring the SBI as a Transmitter or a Receiver Setting SBICR2<TRX> to "1" configures the SBI as a transmitter. Setting <TRX> to "0" configures the SBI as a receiver. At the slave mode: ・...
Page 305 TMPM3V6/M3V4 If SCL bus line is pulled "Low" by other devices when the stop condition is generated, the stop condition is generated after the SCL line is released. SCL line SDA line Stop condition Figure 13-6 Generating the Stop Condition SBISR<BB>...
Page 306 Serial Bus Interface (I2C/SIO) 13.5 Control in the I2C Bus Mode TMPM3V6/M3V4 Up until the point a, Master A and Master B output the same data. At the point a, Master A outputs the "Low" level and Master B outputs the "High" level. Then Master A pulls the SDA bus line to the "Low"...
Page 307 TMPM3V6/M3V4 Internal SCL output MasterA Internal SDA D7A D6A D5A D4A D3A D2A D1A D7A' D6A' D5A' D4A' output Clock output stops here Internal SCL output MasterB InternalSDA Internal SDA output is fixed to "High"level . D7B D6B output due to Arbitration Lost of Master B. <AL>...
Page 308 Serial Bus Interface (I2C/SIO) 13.5 Control in the I2C Bus Mode TMPM3V6/M3V4 13.5.15 Baud Rate Register (SBIBR0) The SBIBR0<I2SBI> register determines if the SBI operates or not when it enters the IDLE mode. This register must be programmed before executing an instruction to switch to the standby mode. 13.5.16 Software Reset If the serial bus interface circuit locks up due to external noise, it can be initialized by using a software reset.
Page 309 TMPM3V6/M3V4 13.6 Data Transfer Procedure in the I2C Bus Mode 13.6.1 Device Initialization Firstly, set SBICR1<ACK><SCK[2:0]>. Set "1" to <ACK> to specify the acknowledgement mode. Set "000" to SBICR1<BC[2:0]> . Secondly, set <SA[6:0]> (a slave address) and <ALS> to SBII2CAR . (In the addressing format mode, set <ALS>="0").
Page 310 Serial Bus Interface (I2C/SIO) 13.6 Data Transfer Procedure in the I2C Bus Mode TMPM3V6/M3V4 Settings in main routine Reg. ← SBISR Reg. ← Reg. e 0x20 if Reg. ≠ 0x00 Ensures that the bus is free. Then SBICR1 ← Selects the acknowledgement mode. SBIDBR ←...
Page 311 TMPM3V6/M3V4 13.6.3 Transferring a Data Word At the end of a data word transfer, the INTSBI interrupt is generated to test <MST> to determine whether the SBI is in the master or slave mode. 13.6.3.1 Master mode (<MST> = "1") Test <TRX>...
Page 312 Serial Bus Interface (I2C/SIO) 13.6 Data Transfer Procedure in the I2C Bus Mode TMPM3V6/M3V4 SCLx pin Write to SBIDBR SDAx pin Acknowledgement from receiver <PIN> INTSBI interrupt request Master output Slave output Figure 13-10 <BC[2:0]>= "000",<ACK>= "1" (Transmitter Mode) Receiver mode (<TRX> = "0") If the next data to be transmitted has eight bits, the transmit data is written into SBIDBR.
Page 313 TMPM3V6/M3V4 In the interrupt processing for terminating the reception of 1-bit data, the stop condition is gener- ated to terminate the data transfer. SCL pin SDA pin Acknowledgment signal to transmitter “High” <PIN> INTSBIinterrupt request Read receive data after clear <ACK> to “0” Read receive data after set <BC[2:0]>...
Page 314 Serial Bus Interface (I2C/SIO) 13.6 Data Transfer Procedure in the I2C Bus Mode TMPM3V6/M3V4 13.6.3.2 Slave mode (<MST> = "0") In the slave mode, the SBI generates the INTSBI interrupt request on four occasions: 1) when the SBI has received any slave address from the master. 2) when the SBI has received a general-call address.
Page 315 TMPM3V6/M3V4 Table 13-2 Processing in Slave Mode <TRX> <AL> <AAS> <ADO> State Processing Arbitration Lost is detected while the slave address was being transmitted and the SBI received a slave address with the direction bit "1" transmitted by an- Set the number of bits in a data word to <BC[2:0]> other master.
Page 316 Serial Bus Interface (I2C/SIO) 13.6 Data Transfer Procedure in the I2C Bus Mode TMPM3V6/M3V4 13.6.4 Generating the Stop Condition When SBISR<BB> is "1", writing "1" to SBICR2<MST, TRX, PIN> and "0" to <BB> causes the SBI to start a sequence for generating the stop condition on the bus. Do not alter the contents of <MST, TRX, BB, PIN>...
Page 317 TMPM3V6/M3V4 "1" is confirmed by following the restart procedure. To check the status of the SCL line, read the port. SBICR2 ← Releases the bus. if SBISR<BB> ≠ 0 Checks that the SCL pin is released. Then if SBISR<LRB> ≠ 1 Checks that no other device is pulling the SCL pin to the "Low".
Page 318 Serial Bus Interface (I2C/SIO) 13.7 Control register of SIO mode TMPM3V6/M3V4 13.7 Control register of SIO mode The following registers control the serial bus interface in the clock-synchronous 8-bit SIO mode and provide its status information for monitoring. 13.7.1 SBICR0(control register 0) bit symbol After reset bit symbol...
Page 319 TMPM3V6/M3V4 13.7.2 SBICR1(Control register 1) bit symbol After reset bit symbol After reset bit symbol After reset bit symbol SIOS SIOINH SIOM After reset 0(Note 1) Bit Symbol Type Function 31-8 Read as 0. SIOS Transfer Start/Stop 0: Stop 1: Start SIOINH Transfer 0: Continue...
Page 320 Serial Bus Interface (I2C/SIO) 13.7 Control register of SIO mode TMPM3V6/M3V4 13.7.3 SBIDBR (Data buffer register) bit symbol After reset bit symbol After reset bit symbol After reset bit symbol After reset Bit Symbol Type Function 31-8 Read as 0. DB[7:0] Receive data Transmit data...
Page 321 TMPM3V6/M3V4 13.7.4 SBICR2(Control register 2) This register serves as SBISR register by writing to it. bit symbol After reset bit symbol After reset bit symbol After reset bit symbol SBIM After reset 1(Note 1) 1(Note 1) 1(Note 1) 1(Note 1) 1(Note 1) 1(Note 1) Bit Symbol...
Page 322 Serial Bus Interface (I2C/SIO) 13.7 Control register of SIO mode TMPM3V6/M3V4 13.7.5 SBISR (Status Register) This register serves as SBICR2 by writing to it. bit symbol After reset bit symbol After reset bit symbol After reset bit symbol SIOF After reset 1(Note) 1(Note) 1(Note)
Page 323 TMPM3V6/M3V4 13.7.6 SBIBR0 (Baud rate register 0) bit symbol After reset bit symbol After reset bit symbol After reset bit symbol I2SBI After reset Bit Symbol Type Function 31-8 Read as 0. Read as 1. I2SBI Operation in IDLE mode. 0: Stop 1: Operate Read as 1.
Page 324 Serial Bus Interface (I2C/SIO) 13.8 Control in SIO mode TMPM3V6/M3V4 13.8 Control in SIO mode 13.8.1 Serial Clock 13.8.1.1 Clock source Internal or external clocks can be selected by programming SBICR1<SCK[2:0]>. Internal clocks In the internal clock mode, one of the seven frequencies can be selected as a serial clock, which is output to the outside through the SCKx pin.
Page 325 TMPM3V6/M3V4 13.8.1.2 Shift Edge Leading-edge shift is used in transmission. Trailing-edge shift is used in reception. Leading-edge shift Data is shifted at the leading edge of the serial clock (or the falling edge of the SCKx pin in- put/output). Trailing-edge shift Data is shifted at the trailing edge of the serial clock (or the rising edge of the SCKx pin in- put/output).
Page 326 Serial Bus Interface (I2C/SIO) 13.8 Control in SIO mode TMPM3V6/M3V4 13.8.2 Transfer Modes The transmit mode, the receive mode or the transmit/receive mode can be selected by programming SBICR1<SIOM[1:0]>. 13.8.2.1 8-bit transmit mode Set the control register to the transmit mode and write the transmit data to SBIDBR. After writing the transmit data, writing "1"...
Page 327 TMPM3V6/M3V4 <SIOS> is cleared <SIOS> <SIOF> <SEF> SCK pin(output) SO pin INTSBI interrupt request SBIDBR (a) Internal clock <SIOS> is cleared. <SIOS> <SIOF> <SEF> SCK pin(input) SO pin INTSBI interrupt request SBIDBR (b)External clock Figure 13-18 Transmit Mode Example: Example of programming (external clock) to terminate transmission by <SIO> if SBISR<SIOF>...
Page 328 Serial Bus Interface (I2C/SIO) 13.8 Control in SIO mode TMPM3V6/M3V4 13.8.2.2 8-bit receive mode Set the control register to the receive mode. Then writing "1" to SBICR1<SIOS> enables reception.Da- ta is taken into the shift register from the SI pin, with the least-significant bit (LSB) first, in synchroniza- tion with the serial clock.
Page 329 TMPM3V6/M3V4 Clear <SIOS> <SIOS> <SIOF> <SEF> SCK pin(output) SI pin INTSBI interrupt request SBIDBR Read receive data Read receive data Figure 13-19 Receive Mode (Example: Internal Clock) 13.8.2.3 8-bit transmit/receive mode Set the control register to the transfer/receive mode. Then writing the transmit data to SBIDBR and set- ting SBICR1<SIOS>...
Page 330 Serial Bus Interface (I2C/SIO) 13.8 Control in SIO mode TMPM3V6/M3V4 <SIOS> is cleared. <SIOS> <SIOF> <SEF> SCK pin(output) SO pin SI pin INTSBI interrupt request SBIDBR Write the transmitted Write the transmitted Read the received Read the received data(a) data(b) data(d) data(c) Figure 13-20 Transmit/Receive Mode (Example: Internal Clock)
Page 331 TMPM3V6/M3V4 14. Synchronous Serial Port (SSP) 14.1 Overview This LSI contains the SSP (Synchronous Serial Port) with 1 channel. This channel has the following features. Three types of synchronous serial ports including the SPI ・ Motorola SPI (SPI) frame format Communication protocol ・...
Page 332 Synchronous Serial Port (SSP) 14.2 Block Diagram TMPM3V6/M3V4 14.2 Block Diagram SSPCLKDIV Clock fsys prescaler Tx/Rx param Write data 16bit 8 [15:0] Transmit TXD[15:0] SPDI APB interface FIFO Transmission/ SPDO Reception logic register SPCLK RXD[15:0] 16bit 8 Read data SPFSS Receive [15:0] FIFO...
Page 333 TMPM3V6/M3V4 14.3 Register 14.3.1 Register List The followings are the SSP control registers and addresses. For detail of the base address, refer to "Address lists of peripheral functions" of "Memory Map" chapter. Base Address = 0x400C_0000 Register Name Address (Base+) Control register 0 SSPCR0 0x0000...
Page 334 Synchronous Serial Port (SSP) 14.3 Register TMPM3V6/M3V4 14.3.2 SSPCR0(Control register 0) bit symbol After Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined bit symbol After Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined bit symbol After Reset bit symbol After Reset Bit Symbol Type...
Page 335 TMPM3V6/M3V4 14.3.3 SSPCR1(Control register1) bit symbol After Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined bit symbol After Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined bit symbol After Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined bit symbol After Reset Undefined...
Page 336 Synchronous Serial Port (SSP) 14.3 Register TMPM3V6/M3V4 14.3.4 SSPDR(Data register) bit symbol After Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined bit symbol After Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined bit symbol DATA After Reset bit symbol DATA After Reset Bit Symbol...
Page 337 TMPM3V6/M3V4 14.3.5 SSPSR(Status register) bit symbol After Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined bit symbol After Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined bit symbol After Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined bit symbol After Reset Undefined...
Page 338 Synchronous Serial Port (SSP) 14.3 Register TMPM3V6/M3V4 14.3.6 SSPCPSR (Clock prescale register) bit symbol After Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined bit symbol After Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined bit symbol After Reset Undefined Undefined Undefined...
Page 339 TMPM3V6/M3V4 14.3.7 SSPIMSC (Interrupt enable/disable register) bit symbol After Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined bit symbol After Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined bit symbol After Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined bit symbol...
Page 340 Synchronous Serial Port (SSP) 14.3 Register TMPM3V6/M3V4 14.3.8 SSPRIS (Pre-enable interrupt status register) bit symbol After Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined bit symbol After Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined bit symbol After Reset Undefined Undefined Undefined...
Page 341 TMPM3V6/M3V4 14.3.9 SSPMIS (Post-enable interrupt status register) bit symbol After Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined bit symbol After Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined bit symbol After Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined...
Page 342 Synchronous Serial Port (SSP) 14.3 Register TMPM3V6/M3V4 14.3.10 SSPICR (Interrupt clear register) bit symbol After Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined bit symbol After Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined bit symbol After Reset Undefined Undefined Undefined...
Page 343 TMPM3V6/M3V4 14.4 Overview of SSP This LSI contains the SSP with 1channels. The SSP is an interface that enables serial communications with the peripheral devices with three types of synchro- nous serial interface functions. The SSP performs serial-parallel conversion of the data received from a peripheral device. The transmit buffers data in the independent 16-bit wide and 8-layered transmit FIFO in the transmit mode, and the receive buffers data in the 16-bit wide and 8-layered receive FIFO in receive mode.
Page 344 Synchronous Serial Port (SSP) 14.4 Overview of SSP TMPM3V6/M3V4 14.4.4 Interrupt generation logic The interrupts, each of which can be masked separately, are generated. A conditional interrupt to occur when the transmit FIFO has free space more than (includ- ing half) of the entire capacity. Transmit interrupt (Number of valid data items in the transmit FIFO ≤...
Page 345 TMPM3V6/M3V4 SPCLK Receive FIFO empty flag During data transfer SSPSR<RNE> Internal down counter enable bit rate Receive timeout interrupt enable SSPIMSC<RTIM> Receive timeout interrupt SSPMIS<RTMIS> Page 323 2019-02-06...
Page 346 Synchronous Serial Port (SSP) 14.4 Overview of SSP TMPM3V6/M3V4 d. Overrun interrupt When the next data (9th data item) is received when the receive FIFO is already full, an overrun interrupt is generated immediately after transfer. The data received after the overrun interrupt is gen- erated (including the 9th data item) will become invalid and be discarded.
Page 347 TMPM3V6/M3V4 14.5 SSP operation 14.5.1 Initial setting for SSP Settings for the SSP communication protocol must be made with the SSP disabled. Control registers SSPCR0 and SSPCR1 need to configure this SSP as a master or slave operating under one of the following protocols. In addition, make the settings related to the communication speed in the clock prescale registers SSPCPSR and SSPCR0 <SCR>.
Page 348 Synchronous Serial Port (SSP) 14.6 Frame Format TMPM3V6/M3V4 14.6 Frame Format Each frame format is between 4 and 16 bits wide depending on the size of data programmed, and is transmitted starting from the MSB. ・ Serial clock (SPCLK) Signals remain "Low" in the SSI and Microwire formats and as inactive in the SPI format while the SSP is in the idle state.
Page 349 TMPM3V6/M3V4 14.6.1 SSI frame format In this mode, the SSP is in idle state, SPCLK and SPFSS are forcedly set to "Low", and the transmit data line SPDO becomes Hi-Z. When data is written in the transmit FIFO, the master outputs "High" pulses of 1 SPCLK to the SPFSS line.
Page 350 Synchronous Serial Port (SSP) 14.6 Frame Format TMPM3V6/M3V4 14.6.2 SPI frame format The SPI interface has 4 lines. SPFSS is used for slave selection. One of the main features of the SPI for- mat is that the <SPO> and <SPH> bits in the SSPCR0 register can be used to set the SPCLK operation timing. SSPCR0 <SPO>...
Page 351 TMPM3V6/M3V4 With this setting <SPO>="0", during the idle period: ・ The SPCLK signal is set to "Low". ・ SPFSS is set to "High". ・ The transmit data line SPDO is set to "Low". If the SSP is enabled and valid data exists in the transmit FIFO, the SPFSS master signal driven by "Low" notifies of the start of transmission.
Page 352 Synchronous Serial Port (SSP) 14.6 Frame Format TMPM3V6/M3V4 14.6.3 Microwire frame format The Microwire format uses a special master/slave messaging method, which operates in half-duplex mode. In this mode, when a frame begins, an 8-bit control message is transmitted to the slave. During this transmis- sion, no incoming data is received by the SSP.
Page 353 TMPM3V6/M3V4 Note: The off-chip slave device can tristate the receive line either on the falling edge of SPCLK after the LSB has been latched by the receive shifter, or when the SPFSS pin goes "High". SPCLK SPFSS SPDO Hi-Z(Note1 Hi-Z(Note1 8bit SPDI Hi-Z(Note2...
Page 354 Synchronous Serial Port (SSP) 14.6 Frame Format TMPM3V6/M3V4 Page 332 2019-02-06...
Page 355 TMPM3V6/M3V4 15. Remote Control Signal Preprocessor (RMC) 15.1 Basic operation Remote control signal preprocessor (hereafter referred to as RMC) receives a remote control signal of which car- rier is removed. 15.1.1 Reception of Remote Control Signal ・ A sampling clock can be selected from either low frequency clock (32.768kHz) or Timer output. ・...
Page 356 Remote Control Signal Preprocessor (RMC) 15.3 Registers TMPM3V6/M3V4 15.3 Registers 15.3.1 Register List Addresses and names of RMC control registers are shown below. Base Address = 0x4004_0400 Register Address(Base+) Enable Register RMCxEN 0x0000 Receive Enable Register RMCxREN 0x0004 Receive Data Buffer Register 1 RMCxRBUF1 0x0008 Receive Data Buffer Register 2...
Page 357 TMPM3V6/M3V4 15.3.2 RMCxEN(Enable Register) bit symbol After reset bit symbol After reset bit symbol After reset bit symbol RMCEN After reset Bit Symbol Type Function 31-2 − Read as 0. − Write as "1". RMCEN Controls RMC operation. 0: Disabled 1: Enabled To allow RMC to function, enable the <RMCEN>...
Page 358 Remote Control Signal Preprocessor (RMC) 15.3 Registers TMPM3V6/M3V4 15.3.3 RMCxREN(Receive Enable Register) bit symbol After reset bit symbol After reset bit symbol After reset bit symbol RMCREN After reset Bit Symbol Type Function 31-1 − Read as 0. RMCREN Reception 0: Disabled 1: Enabled Controls reception of RMC.
Page 359 TMPM3V6/M3V4 15.3.4 RMCxRBUF1(Receive Data Buffer Register 1) bit symbol RMCRBUF(Received data 31 to 24 bit) After reset bit symbol RMCRBUF(Received data 23 to 16 bit) After reset bit symbol RMCRBUF(Received data 15 to 8bit) After reset bit symbol RMCRBUF(Received data 7 to 0 bit) After reset Bit Symbol Type...
Page 360 Remote Control Signal Preprocessor (RMC) 15.3 Registers TMPM3V6/M3V4 15.3.6 RMCxRBUF3(Receive Data Buffer Register 3) bit symbol After reset bit symbol After reset bit symbol After reset bit symbol RMCRBUF(Received data 71 to 64 bit) After reset Bit Symbol Type Function 31-8 Read as 0.
Page 361 TMPM3V6/M3V4 15.3.7 RMCxRCR1(Receive Control Register 1) bit symbol RMCLCMAX After reset bit symbol RMCLCMIN After reset bit symbol RMCLLMAX After reset bit symbol RMCLLMIN After reset Bit Symbol Type Function 31-24 RMCLCMAX[7:0] Specifies a maximum cycle of leader detection. Calculating formula of the maximum cycle: <RMCLCMAX> × 4/fs [s]. 23-16 RMCLCMIN[7:0] Specifies a minimum cycle of leader detection.
Page 362 Remote Control Signal Preprocessor (RMC) 15.3 Registers TMPM3V6/M3V4 15.3.8 RMCxRCR2(Receive Control Register 2) bit symbol RMCLIEN RMCEDIEN RMCLD RMCPHM After reset bit symbol After reset bit symbol RMCLL After reset bit symbol RMCDMAX After reset Bit Symbol Type Function RMCLIEN Leader detection interrupt 0: Not generated 1: Generated...
Page 363 TMPM3V6/M3V4 15.3.9 RMCxRCR3(Receive Control Register 3) bit symbol After reset bit symbol After reset bit symbol RMCDATH After reset bit symbol RMCDATL After reset Bit Symbol Type Function 31-15 Read as 0. 14-8 RMCDATH[6:0] Larger threshold to determine a signal pattern in a phase method Calculating formula of the threshold: <RMCDATH>...
Page 364 Remote Control Signal Preprocessor (RMC) 15.3 Registers TMPM3V6/M3V4 15.3.10 RMCxRCR4(Receive Control Register 4) bit symbol After reset bit symbol After reset bit symbol After reset bit symbol RMCPO RMCNC After reset Bit Symbol Type Function 31-8 − Read as 0. RMCPO Remote control input signal 0: Not reversed...
Page 365 TMPM3V6/M3V4 15.3.11 RMCxRSTAT(Receive Status Register) bit symbol After reset bit symbol After reset bit symbol RMCRLIF RMCLOIF RMCDMAXIF RMCEDIF After reset bit symbol RMCRLDR RMCRNUM After reset Bit Symbol Type Function 31-16 − Read as 0. RMCRLIF Interrupt source flag 0: No leader detection interrupt generated.
Page 366 Remote Control Signal Preprocessor (RMC) 15.3 Registers TMPM3V6/M3V4 15.3.12 RMCxEND1(Receive End bit Number Register 1) bit symbol After reset bit symbol After reset bit symbol After reset bit symbol RMCEND1 After reset Bit Symbol Type Function 31-7 Read as 0. RMCEND1[6:0] Specifies that the number of receive data bit 000_0000 : No specifically the receive data bit...
Page 367 TMPM3V6/M3V4 15.3.14 RMCxEND3(Receive End bit Number Register 3) bit symbol After reset bit symbol After reset bit symbol After reset bit symbol RMCEND3 After reset Bit Symbol Type Function 31-7 Read as 0. RMCEND3[6:0] Specifies the number of receive data bit 000_0000 : No specifically the receive data bit 000_0001 to 100_1000 : Specifies that the number of receive data bit(1 to 72bit) 100_1001 to 111_1111 : Don’t set the value...
Page 368 Remote Control Signal Preprocessor (RMC) 15.3 Registers TMPM3V6/M3V4 15.3.15 RMCxFSSEL(Source Clock selection Register) bit symbol After reset bit symbol After reset bit symbol After reset bit symbol RMCCLK After reset Bit Symbol Type Function 31-1 Read as 0. RMCCLK Specifies that Sampling clock of RMC function 0 : Low frequency Clock (32.768kHz) 1 : Timer output (TBxOUT) For the Sampling of RMC function, It is able to set the Low Frequency Clock (32.768kHz) or Timer output...
Page 369 TMPM3V6/M3V4 15.4 Operation Description 15.4.1 Reception of Remote Control Signal 15.4.1.1 Sampling clock A remote control signal is sampled by using low-speed 32.768kHz clock (fs) or TBxOUT which is out- put of 16bit Timer/Event counters. The sampling clock is configurable using RMCxFSSEL<RMCCLK>. For the information of TBxOUT used for sampling clock, refer to Chapter "Product Information".
Page 370 Remote Control Signal Preprocessor (RMC) 15.4 Operation Description TMPM3V6/M3V4 15.4.1.3 Preparation Before starting receiving process, configure how to receive remote control signal using the Remote Con- trol Signal Receive Control Registers (RMCxRCR1, RMCxRCR2 and RMCxRCR3, RMCxRCR4). Settings of Noise Cancelling Time Configure noise cancelling time with the RMCxRCR4 <RMCNC[3:0]>.
Page 371 TMPM3V6/M3V4 Settings of Detecting Leader Set the leader cycle and a "Low" width of the leader to RMCxRCR1 <RMCLLMIN[7:0]> <RMCLLMAX[7:0]> <RMCLCMIN[7:0]> <RMCLCMAX[7:0]>. When you configure those above, follow the rule shown below. Leader Rules <RMCLCMAX[7:0]> > <RMCLCMIN[7:0]> "Low" width + <RMCLLMAX[7:0]>...
Page 372 Remote Control Signal Preprocessor (RMC) 15.4 Operation Description TMPM3V6/M3V4 Setting of 0/1 determination data bit Based on a falling edge cycle, the data bit of a cycle modulation is determined as 0 or 1. There are two kinds of determinations: As for data bit determination of a remote control signal in a phase method, see"15.4.1.8 Receiv- ing a Remote Control Signal in a Phase Method".
Page 373 TMPM3V6/M3V4 Settings of Reception Completion To complete data reception, settings of detecting the maximum data bit cycle and excess "Low" width are required. If multiple factors are specified, reception is completed by the factor detected first. Make sure to configure the reception completion settings. 1.
Page 374 Remote Control Signal Preprocessor (RMC) 15.4 Operation Description TMPM3V6/M3V4 2. Completion by detecting "Low" width To complete reception by detecting the "Low" width, you need to configure the RMCxRCR2 <RMCLL[7:0]>. After the falling edge of the data bit is detected, if the signal stays "Low" longer than speci- fied, excess "Low"...
Page 375 TMPM3V6/M3V4 15.4.1.4 Enabling Reception By enabling the RMCxREN <RMCREN> after configuring the RMCxRCR1, RMCxRCR2, RMCxRCR3 and RMCxRCR4 registers, RMC is ready for reception. Detecting a leader initiates reception. Note: Changing the configurations of the RMCxRCR1, RMCxRCR2, RMCxRCR3 and RMCxRCR4 regis- ters during reception may harm their proper operation.
Page 376 Remote Control Signal Preprocessor (RMC) 15.4 Operation Description TMPM3V6/M3V4 15.4.1.7 A Leader only with "Low" Width The figure shown below illustrates a remote control signal that starts with a leader of which waveform on- ly has "Low" width. This signal starts with a leader that only has "Low" width and a data bit cycle starts from the rising edge.
Page 377 TMPM3V6/M3V4 15.4.1.8 Receiving a Remote Control Signal in a Phase Method RMC is capable of receiving a remote control signal in a phase method of which signal cycle is fixed. A signal in the phase method has three waveform patterns (see the figure shown below). By setting two thresholds a remote control signal pattern is determined.
Page 378 Remote Control Signal Preprocessor (RMC) 15.4 Operation Description TMPM3V6/M3V4 Remote control signal The first two bits of data need to be “11”. Figure 15-11 The waveform pattern in phase method Page 356 2019-02-06...
Page 379 TMPM3V6/M3V4 16. Analog/Digital Converter (ADC) The TMPM3V6/M3V4 contains a 12-/10- (selectable) bit successive-approximation analog-to-digital converter (ADC). External analog input pins (AIN0 to AIN17) can also be used as input/output ports. 16.1 Functions and features 1. It can select analog input and start AD conversion when receiving trigger signal from TMRB(interrupt). 2.
Page 380 Analog/Digital Converter (ADC) 16.3 List of Registers TMPM3V6/M3V4 16.3 List of Registers Base Address = 0x4003_0000 Register Name Address(Base+) Clock Setting Register ADCLK 0x0000 Mode Setting Register 0 ADMOD0 0x0004 Mode Setting Register 1 ADMOD1 0x0008 Mode Setting Register 2 ADMOD2 0x000C Monitoring Setting Register 0...
Page 381 TMPM3V6/M3V4 16.4 Register Descriptions AD conversion is performed at the clock frequency selected in the ADC Clock Setting Register. 16.4.1 ADCLK (Clock Setting Register) bit symbol After reset bit symbol After reset bit symbol After reset bit symbol ADCLK After reset Bit Symbol Type Function...
Page 382 Analog/Digital Converter (ADC) 16.4 Register Descriptions TMPM3V6/M3V4 16.4.2 ADMOD0 (Mode Setting Register 0) bit symbol After reset bit symbol After reset bit symbol After reset bit symbol DACON ADSS After reset Bit Symbol Type Function 31-2 − Read as "0". DACON ADC operation control 1 0: Stop...
Page 383 TMPM3V6/M3V4 16.4.3 ADMOD1 (Mode Setting Register 1) bit symbol After reset bit symbol After reset bit symbol After reset bit symbol ADEN ADAS After reset Bit Symbol Type Function 31-8 − Read as "0". ADEN AD conversion control 0: Disable 1: Enable Setting <ADEN>...
Page 384 Analog/Digital Converter (ADC) 16.4 Register Descriptions TMPM3V6/M3V4 16.4.4 ADMOD2 (Mode Setting Register 2) bit symbol After reset bit symbol After reset bit symbol After reset bit symbol ADSFN ADBFN After reset Bit Symbol Type Function 31-2 − Read as "0". ADSFN Software conversion busy flag 0: Conversion completed...
Page 385 TMPM3V6/M3V4 16.4.5 ADMOD3 (Mode Setting Register 3) bit symbol After reset bit symbol After reset bit symbol BITS RCUT After reset bit symbol PMODE After reset Bit Symbol Type Function 31-16 − Read as "0". 15-12 − Write as "0". 11-10 BITS[1:0] 12-bit/10-bit resolution mode selection...
Page 386 Analog/Digital Converter (ADC) 16.4 Register Descriptions TMPM3V6/M3V4 16.4.6 ADCMPCR0(Monitoring Setting Register 0) After fixing the conversion result, the interrupt signal (INTADCP) is generated. bit symbol After reset bit symbol After reset bit symbol CMPCNT0 After reset bit symbol CMP0EN ADBIG0 REGS0 After reset Bit Symbol...
Page 387 TMPM3V6/M3V4 16.4.7 ADCMPCR1(Monitoring Setting Register 1) After fixing the conversion result, the interrupt signal (INTADCP) is generated. bit symbol After reset bit symbol After reset bit symbol CMPCNT1 After reset bit symbol CMP1EN ADBIG1 REGS1 After reset Bit Symbol Type Function 31-12 Read as "0".
Page 388 Analog/Digital Converter (ADC) 16.4 Register Descriptions TMPM3V6/M3V4 16.4.8 ADCMP0(Conversion Result Compare Register 0) bit symbol After reset bit symbol After reset bit symbol AD0CMP After reset bit symbol AD0CMP After reset Bit Symbol Type Function 31-16 Read as "0". 15-4 AD0CMP[11:0] The value to be compared with an AD conversion result Specify the value to be compared with an AD conversion result.
Page 389 TMPM3V6/M3V4 16.4.10 ADREG0(Conversion Result Register 0) bit symbol After reset bit symbol After reset bit symbol ADR0 After reset bit symbol ADR0 OVR0 ADR0RF After reset Bit Symbol Type Function 31-16 Read as "0". 15-4 ADR0[11:0] The value of an AD conversion result Read as "0".
Page 390 Analog/Digital Converter (ADC) 16.4 Register Descriptions TMPM3V6/M3V4 16.4.11 ADREG1(Conversion Result Register 1) bit symbol After reset bit symbol After reset bit symbol ADR1 After reset bit symbol ADR1 OVR1 ADR1RF After reset Bit Symbol Type Function 31-16 Read as "0". 15-4 ADR1[11:0] The value of an AD conversion result...
Page 391 TMPM3V6/M3V4 16.4.12 ADREG2(Conversion Result Register 2) bit symbol After reset bit symbol After reset bit symbol ADR2 After reset bit symbol ADR2 OVR2 ADR2RF After reset Bit Symbol Type Function 31-16 Read as "0". 15-4 ADR2[11:0] The value of an AD conversion result Read as "0".
Page 392 Analog/Digital Converter (ADC) 16.4 Register Descriptions TMPM3V6/M3V4 16.4.13 ADREG3(Conversion Result Register 3) bit symbol After reset bit symbol After reset bit symbol ADR3 After reset bit symbol ADR3 OVR3 ADR3RF After reset Bit Symbol Type Function 31-16 Read as "0". 15-4 ADR3[11:0] The value of an AD conversion result...
Page 393 TMPM3V6/M3V4 16.4.14 ADREG4(Conversion Result Register 4) bit symbol After reset bit symbol After reset bit symbol ADR4 After reset bit symbol ADR4 OVR4 ADR4RF After reset Bit Symbol Type Function 31-16 Read as "0". 15-4 ADR4[11:0] The value of an AD conversion result Read as "0".
Page 394 Analog/Digital Converter (ADC) 16.4 Register Descriptions TMPM3V6/M3V4 16.4.15 ADREG5(Conversion Result Register 5) bit symbol After reset bit symbol After reset bit symbol ADR5 After reset bit symbol ADR5 OVR5 ADR5RF After reset Bit Symbol Type Function 31-16 Read as "0". 15-4 ADR5[11:0] The value of an AD conversion result...
Page 395 TMPM3V6/M3V4 16.4.16 ADREG6(Conversion Result Register 6) bit symbol After reset bit symbol After reset bit symbol ADR6 After reset bit symbol ADR6 OVR6 ADR6RF After reset Bit Symbol Type Function 31-16 Read as "0". 15-4 ADR6[11:0] The value of an AD conversion result Read as "0".
Page 396 Analog/Digital Converter (ADC) 16.4 Register Descriptions TMPM3V6/M3V4 16.4.17 ADREG7(Conversion Result Register 7) bit symbol After reset bit symbol After reset bit symbol ADR7 After reset bit symbol ADR7 OVR7 ADR7RF After reset Bit Symbol Type Function 31-16 Read as "0". 15-4 ADR7[11:0] The value of an AD conversion result...
Page 397 TMPM3V6/M3V4 16.4.18 ADREG8(Conversion Result Register 8) bit symbol After reset bit symbol After reset bit symbol ADR8 After reset bit symbol ADR8 OVR8 ADR8RF After reset Bit Symbol Type Function 31-16 Read as "0". 15-4 ADR8[11:0] The value of an AD conversion result Read as "0".
Page 398 Analog/Digital Converter (ADC) 16.4 Register Descriptions TMPM3V6/M3V4 16.4.19 ADREG9(Conversion Result Register 9) bit symbol After reset bit symbol After reset bit symbol ADR9 After reset bit symbol ADR9 OVR9 ADR9RF After reset Bit Symbol Type Function 31-16 Read as "0". 15-4 ADR9[11:0] The value of an AD conversion result...
Page 399 TMPM3V6/M3V4 16.4.20 ADREG10(Conversion Result Register 10) bit symbol After reset bit symbol After reset bit symbol ADR10 After reset bit symbol ADR10 OVR10 ADR10RF After reset Bit Symbol Type Function 31-16 Read as "0". 15-4 ADR10[11:0] The value of an AD conversion result Read as "0".
Page 400 Analog/Digital Converter (ADC) 16.4 Register Descriptions TMPM3V6/M3V4 16.4.21 ADREG11(Conversion Result Register 11) bit symbol After reset bit symbol After reset bit symbol ADR11 After reset bit symbol ADR11 OVR11 ADR11RF After reset Bit Symbol Type Function 31-16 Read as "0". 15-4 ADR11[11:0] The value of an AD conversion result...
Page 401 TMPM3V6/M3V4 16.4.22 ADTSET03 / ADTSET47 / ADTSET811 (Timer Trigger Program Registers) AD conversion can be started by INTTB51 generated from Timer5(TMRB5) as a trigger. There are twelve 8-bit registers for programming timer triggers. Setting the <ENSTm> to "1" enables the ADTSETm register. The <AINSTm[4:0]>...
Page 402 Analog/Digital Converter (ADC) 16.4 Register Descriptions TMPM3V6/M3V4 Bit Symbol Type Function ENST3 ADREG3 enable 0:Disable 1:Enable 30-29 Read as "0". 28-24 AINST3[4:0] AIN select Refer to "Table 16-1 Select the AIN pin". ENST2 ADREG2 enable 0:Disable 1:Enable 22-21 Read as "0". 20-16 AINST2[4:0] AIN select...
Page 403 TMPM3V6/M3V4 ADTSET47: Timer Trigger Program Registers 47 bit symbol ENST7 AINST7 After reset bit symbol ENST6 AINST6 After reset bit symbol ENST5 AINST5 After reset bit symbol ENST4 AINST4 After reset Bit Symbol Type Function ENST7 ADREG7 enable 0:Disable 1:Enable 30-29 Read as "0".
Page 404 Analog/Digital Converter (ADC) 16.4 Register Descriptions TMPM3V6/M3V4 ADTSET811: Timer Trigger Program Registers 811 bit symbol ENST11 AINST11 After reset bit symbol ENST10 AINST10 After reset bit symbol ENST9 AINST9 After reset bit symbol ENST8 AINST8 After reset Bit Symbol Type Function ENST11 ADREG11 enable...
Page 405 TMPM3V6/M3V4 16.4.23 ADSSET03 / ADSSET47 / ADSSET811( Software Trigger Program Registers ) AD conversion can be started by software. There are twelve 8-bit registers for programming software trig- gers. The numbers of the Software Trigger Program Registers correspond to those of the Conversion Result Reg- isters.
Page 406 Analog/Digital Converter (ADC) 16.4 Register Descriptions TMPM3V6/M3V4 Bit Symbol Type Function ENSS3 ADREG3 enable 0:Disable 1:Enable 30-29 Read as "0". 28-24 AINSS3[4:0] AIN select Refer to "Table 16-2 Select the AIN pin". ENSS2 ADREG2 enable 0:Disable 1:Enable 22-21 Read as "0". 20-16 AINSS2[4:0] AIN select...
Page 407 TMPM3V6/M3V4 ADSSET47: Software Trigger Program Registers 47 bit symbol ENSS7 AINSS7 After reset bit symbol ENSS6 AINSS6 After reset bit symbol ENSS5 AINSS5 After reset bit symbol ENSS4 AINSS4 After reset Bit Symbol Type Function ENSS7 ADREG7 enable 0:Disable 1:Enable 30-29 Read as "0".
Page 408 Analog/Digital Converter (ADC) 16.4 Register Descriptions TMPM3V6/M3V4 ADSSET811: Software Trigger Program Registers 811 bit symbol ENSS11 AINSS11 After reset bit symbol ENSS10 AINSS10 After reset bit symbol ENSS9 AINSS9 After reset bit symbol ENSS8 AINSS8 After reset Bit Symbol Type Function ENSS11 ADREG11 enable...
Page 409 TMPM3V6/M3V4 16.4.24 ADASET03 / ADASET47 / ADASET811( Constant Conversion Program Regis- ters ) The ADCs allow conversion triggers to be constantly enabled. There are twelve 8-bit registers for program- ming constant triggers. Setting the <ENSAm> to "1" enables the ADASETm register. The <AINSAm[4:0]> are used to select the AIN pin to be used.
Page 410 Analog/Digital Converter (ADC) 16.4 Register Descriptions TMPM3V6/M3V4 ADASET03: Constant Conversion Program Registers03 bit symbol ENSA3 AINSA3 After reset bit symbol ENSA2 AINSA2 After reset bit symbol ENSA1 AINSA1 After reset bit symbol ENSA0 AINSA0 After reset Bit Symbol Type Function ENSA3 ADREG3 enable 0:Disable...
Page 411 TMPM3V6/M3V4 ADASET47: Constant Conversion Program Registers 47 bit symbol ENSA7 AINSA7 After reset bit symbol ENSA6 AINSA6 After reset bit symbol ENSA5 AINSA5 After reset bit symbol ENSA4 AINSA4 After reset Bit Symbol Type Function ENSA7 ADREG7 enable 0:Disable 1:Enable 30-29 Read as "0".
Page 412 Analog/Digital Converter (ADC) 16.4 Register Descriptions TMPM3V6/M3V4 ADASET811: Constant Conversion Program Registers 811 bit symbol ENSA11 AINSA11 After reset bit symbol ENSA10 AINSA10 After reset bit symbol ENSA9 AINSA9 After reset bit symbol ENSA8 AINSA8 After reset Bit Symbol Type Function ENSA11 ADREG11 enable...
Page 413 TMPM3V6/M3V4 16.5 Operation Descriptions 16.5.1 Analog Reference Voltages For the High-level and Low-level analog reference voltages, the AVDD5and AVSSpins are used . If AD- MOD3<RCUT> is set to "1", current flowing between AVDD5 and AVSS can be controlled to reduce consumption current.
Page 414 Analog/Digital Converter (ADC) 16.5 Operation Descriptions TMPM3V6/M3V4 Trigger 1st conversion 2nd conversion Busy flag <ADBFN> AD conversion result Result of 1st conversion (ADREG0) register0(ADxREG0) (ADxREG0) AD conversion result Result of 2nd conversion (ADREG1) register1(ADxREG1) (ADxREG1) Delay time Delay time AD conversion time AD conversion time from trigger to the next...
Page 415 TMPM3V6/M3V4 16.6 Timing chart of AD conversion The following shows a timing chart of software trigger conversion, constant conversion and acceptance of trigger. 16.6.1 Software trigger Conversion In the software trigger conversion, the interrupt is generated after completion of conversion programmed by ADSSET03, ADSSET47 and ADSSET811.(Figure 16-3) If the ADMOD1<ADEN>...
Page 416 Analog/Digital Converter (ADC) 16.6 Timing chart of AD conversion TMPM3V6/M3V4 Condition Software trigger setting : AINA0, AINA1, AINA2 AINA0, AINA1, AINA2 AIN0, AIN1, AIN2 AD conversion Enable/Disable <ADEN> <ADSFN> is cleared to “0” immediately after clearing <ADEN> to “0” . Software trigger conversion (<ADSS>="1")
Page 417 TMPM3V6/M3V4 16.6.2 Constant Conversion In the constant conversion, if the next conversion completes without reading the previous result from the con- version result register, the overrun flag is set to "1". In this case, the previous conversion result in the conver- sion result register is overwritten by the next result.
Page 418 Analog/Digital Converter (ADC) 16.6 Timing chart of AD conversion TMPM3V6/M3V4 16.6.3 AD conversion by trigger When the timer trigger is occurred during the software trigger conversion, the ongoing conversion stops immediately and start AD conversion correspond to timer trigger.(Figure 16-6) After the completion of conversion by timer trigger, the software trigger conversion starts from the beginning programmed setting.
Page 419 TMPM3V6/M3V4 Page 397 2019-02-06...
Page 420 Analog/Digital Converter (ADC) 16.6 Timing chart of AD conversion TMPM3V6/M3V4 Page 398 2019-02-06...
Page 421 TMPM3V6/M3V4 17. Real Time Clock (RTC) 17.1 Function 1. Clock (hour, minute and second) 2. Calendar (month, week, date and leap year) 3. Selectable 12 (am/ pm) and 24 hour display 4. Time adjustment + or − 30 seconds (by software) 5.
Page 422 Real Time Clock (RTC) 17.3 Detailed Description Register TMPM3V6/M3V4 17.3 Detailed Description Register 17.3.1 Register List The registers and the addresses related to RTC are shown as below. RTC has two functions, PAGE0 (clock) and PAGE1 (alarm), which share some parts of registers. The PAGE can be selected by setting RTCPAGER<PAGE >.
Page 423 TMPM3V6/M3V4 Table 17-1 PAGE0 (clock function) register Symbol Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Function RTCSECR − 40sec. 20sec. 10sec. 8sec. 4sec. 2sec. 1sec. Second column RTCMINR − 40min. 20min. 10min. 8min. 4min. 2min. 1min. Minute column 20hours RTCHOURR −...
Page 424 Real Time Clock (RTC) 17.3 Detailed Description Register TMPM3V6/M3V4 17.3.3 Detailed Description of Control Register 17.3.3.1 RTCSECR (Second column register (for PAGE0 only)) bit symbol After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Bit Symbol Type Function − Read as 0. Setting digit register of second 000_0000 : 00sec.
Page 425 TMPM3V6/M3V4 17.3.3.3 RTCHOURR (Hour column register(PAGE0/1)) 24-hour clock mode (RTCMONTHR<MO0>= "1") Bit symbol After reset Undefined Undefined Undefined Undefined Undefined Undefined Bit Symbol Type Function − Read as 0. Setting digit register of Hour. 00_0000 : 0 o’clock 01_0000 : 10 o’clock 10_0000 : 20 o’clock 00_0001 : 1 o’clock 01_0001 : 11 o’clock...
Page 426 Real Time Clock (RTC) 17.3 Detailed Description Register TMPM3V6/M3V4 17.3.3.4 RTCDAYR (Day of the week column register(PAGE0/1)) Bit symbol After reset Undefined Undefined Undefined Bit Symbol Type Function − Read as 0. Setting digit register of day of the week. 000: Sunday 111: don’t care (Only PAGE1) 001: Monday...
Page 427 TMPM3V6/M3V4 17.3.3.6 RTCMONTHR (Month column register (for PAGE0 only)) Bit symbol After reset Undefined Undefined Undefined Undefined Undefined Bit Symbol Type Function − Read as 0. Setting digit register of Month. 0_0001 : January 0_0111 : July 0_0010 : February 0_1000 : August 0_0011 :...
Page 428 Real Time Clock (RTC) 17.3 Detailed Description Register TMPM3V6/M3V4 17.3.3.8 RTCYEARR (Year column register (for PAGE0 only)) bit symbol After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Bit Symbol Type Function Setting digit register of Year. 0000_0000 : 00 year 0001_0000 : 10 years 0110_0000 : 60 years 0000_0001 : 01 years...
Page 429 TMPM3V6/M3V4 17.3.3.10 RTCPAGER(PAGE register(PAGE0/1)) Bit symbol INTENA ADJUST ENATMR ENAALM PAGE After reset Undefined Undefined Bit Symbol Type Function INTENA INTRTC 0:Disable 1:Enable − Read as 0. ADJUST [Write] 0: Don't care 1: Sets ADJUST request Adjusts seconds. The request is sampled when the sec. counter counts up. If the time elapsed is between 0 and 29 seconds, the sec.
Page 430 Real Time Clock (RTC) 17.3 Detailed Description Register TMPM3V6/M3V4 17.3.3.11 RTCRESTR (Reset register (for PAGE0/1)) Bit symbol DIS1HZ DIS16HZ RSTTMR RSTALM DIS2HZ DIS4HZ DIS8HZ After reset Bit Symbol Type Function DIS1HZ 1 Hz 0:Enable 1: Disable DIS16HZ 16 Hz 0: Enable 1: Disable RSTTMR [Write]...
Page 431 TMPM3V6/M3V4 Table 17-3 Select interrupt source signal RTCPAGER <DIS1HZ> <DIS2HZ> <DIS4HZ> <DIS8HZ> <DIS16HZ> Interrupt source signal <ENAALM> ALARM 1 Hz 2 Hz 16 Hz Others Interrupt not generated Page 409 2019-02-06...
Page 432 Real Time Clock (RTC) 17.4 Operational Description TMPM3V6/M3V4 17.4 Operational Description The RTC incorporates a second counter that generates a 1Hz signal from a 32.768 kHz signal. The second counter operation must be taken into account when using the RTC. Note: After reset, a low-speed clock stops oscillation.
Page 433 TMPM3V6/M3V4 Write data after resetting the second counter. The 1Hz-interrupt is generated one second after enabling the interrupt subsequent to counter reset. The time must be set within one second after the interrupt. Start RTCPAGER<PAGE> = "0" then select PAGE0 RTCRESTR<RSTTMR>...
Page 434 Real Time Clock (RTC) 17.4 Operational Description TMPM3V6/M3V4 17.4.3 Entering the Low Power Consumption Mode To enter SLEEP mode, in which the system clock stops, after changing clock data, adjusting seconds or re- setting the clock, be sure to observe one of the following procedures 1.
Page 435 TMPM3V6/M3V4 17.5 Alarm function By writing "1" to RTCPAGER<PAGE>, the alarm function of the PAGE1 registers is enabled. One of the follow- ing three signals is output to the ALARM pin. 1. "Low" pulse (when the alarm register corresponds with the clock) 2.
Page 436 Real Time Clock (RTC) 17.5 Alarm function TMPM3V6/M3V4 17.5.2 Outputting Low-pulse (1 Hz, 2 Hz, 4 Hz, 8 Hz or 16 Hz) When RTCPAGER<ENAALM> and RTCRESTR are set as Table 17-3 and then RTCPAGER<INTENA> = "1" is set, one cycle low-speed (1 Hz, 2 Hz, 4 Hz, 8 Hz or 16 Hz) low pulse is output to ALARM pin. At the same time, INTRTC interrupt is also output.
Page 437 TMPM3V6/M3V4 18. Power-on-Reset Circuit (POR) The power-on-reset circuit (POR) generates a power-on reset signal when power-on. Power supply voltage is indicated as RVDD5. 18.1 Structure Power-on-reset circuit consists of the reference voltage generation circuit, comparators, the VLTD reset circuit and the power-on counter. This circuit compares a voltage divided by the ladder resistor with a reference voltage generated in the refer- ence voltage generation circuit in the comparator.
Page 438 Power-on-Reset Circuit (POR) 18.2 Function TMPM3V6/M3V4 18.2 Function At power-on, a power-on detection signal generates while power supply voltage is lower than the releasing volt- age. Power-on detection signal is released at the timing when RVDD5 is over 3.0 ±0.2 V. When the power-on detection signal is released and the VLTD reset signal is also released, the power-on counter starts to operate.
Page 439 TMPM3V6/M3V4 19. Low Voltage Detection Circuit (VLTD) The low voltage detection circuit generates a reset signal by detecting a decreasing voltage. Note: Due to the fluctuation of supply voltage, the voltage detection circuit may not operate properly. Users should give due consideration based on the electrical characteristic in the device designing. 19.1 Structure The low voltage detection circuit consists of a reference voltage generation circuit, a detection voltage level selec-...
Page 440 Low Voltage Detection Circuit (VLTD) 19.2 Registers TMPM3V6/M3V4 19.2 Registers 19.2.1 Register List Base Address = 0x4004_0900 Register name Address(Base+) Voltage detection control register VDCR 0x0000 19.2.2 VDCR (Voltage detection control register) bit symbol − − − − − − −...
Page 441 TMPM3V6/M3V4 19.3 Operation Description 19.3.1 Control The voltage detection circuit is controlled by voltage detection control registers. 19.3.2 Function Enabling/disabling the voltage detection can be programmed by VDCR<VDEN>. After the voltage detec- tion operation is enabled, When the supply voltage becomes lower than the detection voltage (4.1 ± 0.2V), a voltage detection reset signal is generated.
Page 442 Low Voltage Detection Circuit (VLTD) 19.3 Operation Description TMPM3V6/M3V4 Symbol Parameter Unit tVDEN Setup time after enabling VLTD tVDDT1 Voltage detection response time μs tVDDT2 Voltage detection releasing time‘ tVDPW Voltage detection minimum pulse width LDLVL Detection voltage Symbol Parameter Unit tPWUP Power-on Counter...
Page 443 TMPM3V6/M3V4 20. Oscillation Frequency Detector (OFD) The oscillation frequency detector circuit (OFD) detects abnormal clock frequency. To use the OFD, abnormal states of clock such as a harmonic, a sub harmonic or stopped state can be detected. The OFD monitors the target clock frequency using reference frequency and generates a reset signal if abnor- mal state is detected.
Page 444 Oscillation Frequency Detector (OFD) 20.2 Registers TMPM3V6/M3V4 20.2 Registers 20.2.1 Register List Base Address = 0x4004_0800 Register name Address (Base+) Control register 1 OFDCR1 0x0000 Control register 2 OFDCR2 0x0004 Lower detection frequency setting register OFDMN 0x0008 Reserved 0x000C Higher detection frequency setting register OFDMX 0x0010 Reserved...
Page 445 TMPM3V6/M3V4 20.2.1.1 OFDCR1 (Control register 1) bit symbol After reset bit symbol After reset bit symbol After reset bit symbol OFDWEN After reset Bit Symbol Type Description 31-8 − Read as 0. OFDWEN[7:0] Controls register write 0x06: Disable 0xF9: Enable Setting 0xF9 enables to write registers except OFDCR1.
Page 446 Oscillation Frequency Detector (OFD) 20.2 Registers TMPM3V6/M3V4 20.2.1.2 OFDCR2 (Control register 2) bit symbol After reset bit symbol After reset bit symbol After reset bit symbol OFDEN After reset Bit Symbol Type Description 31-8 − Read as 0. OFDEN[7:0] Controls frequency detecting. 0x00: Disable 0xE4: Enable Writing a value except 0x00 or 0xE4 is invalid and a value will not be changed.
Page 447 TMPM3V6/M3V4 20.2.1.3 OFDMN (Lower detection frequency setting register) bit symbol After reset bit symbol After reset bit symbol After reset bit symbol OFDMN After reset Bit Symbol Type Description 31-8 − Read as 0. OFDMN[7:0] Sets lower detection frequency. Note: Writing to the register of OFDMN is protected while OFD circuit is operating. 20.2.1.4 OFDMX (Higher detection frequency setting register) bit symbol...
Page 448 Oscillation Frequency Detector (OFD) 20.2 Registers TMPM3V6/M3V4 20.2.1.5 OFDRST (Reset control register) bit symbol After reset bit symbol After reset bit symbol After reset bit symbol OFDRSTEN After reset Bit Symbol Type Description 31-1 − Read as 0. OFDRSTEN Controls generating a reset. 0: Disable 1: Enable Note: Writing to the register of OFDRST is protected while OFD circuit is operating.
Page 449 TMPM3V6/M3V4 20.2.1.6 OFDSTAT (Status register) bit symbol After reset bit symbol After reset bit symbol After reset bit symbol OFDBUSY FRQERR After reset Bit Symbol Type Description 31-2 − Read as 0. OFDBUSY OFD operation 0: Stop 1: Run FRQERR Error detecting flag 0: No Error 1: Error...
Page 450 Oscillation Frequency Detector (OFD) 20.3 Operational Description TMPM3V6/M3V4 20.3 Operational Description 20.3.1 Setting All register except OFDCR1 can not be written by reset. They are can be written by writing "0xF9" to OFDCR1. To protect the mistaken writing, should be written "0x06" to OFDCR1 after setting all registers. And the reg- ister should be modified when OFD is stopped.
Page 451 TMPM3V6/M3V4 20.3.3 Detection Frequency The detection frequency have a detection frequency range and an undetectable frequency range because of oscillation accuracy. Therefore, it is undefined whether to be detected between detection frequency range and undetectable it. Figure 20-2 shows the detection or undetectable frequency range when the target clock error is ±10% and the reference clock error is ±...
Page 452 Oscillation Frequency Detector (OFD) 20.3 Operational Description TMPM3V6/M3V4 20.3.5 Example of Operational Procedure The example of operational procedure is shown below. After reset, confirms various reset factor by CGRSTFLG. If the reset factor is not by the oscillation frequen- cy detect, enable external oscillation, set register to use OFD and enable operation. Reset output must be disa- bled at this time.
Page 453 TMPM3V6/M3V4 21. Watchdog Timer(WDT) The watchdog timer (WDT) is for detecting malfunctions (runaways) of the CPU caused by noises or other distur- bances and remedying them to return the CPU to normal operation. If the watchdog timer detects a runaway, it generates a INTWDT interrupt or reset. Note: INTWDT interrupt is a factor of the non-maskable interrupts (NMI).
Page 454 Watchdog Timer(WDT) 21.2 Register TMPM3V6/M3V4 21.2 Register The followings are the watchdog timer control registers and addresses. Base Address = 0x4004_0000 Register name Address(Base+) Watchdog Timer Mode Register WDMOD 0x0000 Watchdog Timer Control Register WDCR 0x0004 21.2.1 WDMOD(Watchdog Timer Mode Register) bit symbol After reset bit symbol...
Page 455 TMPM3V6/M3V4 Table 21-1 Detection time of watchdog timer (fc = 40MHz) WDMOD<WDTP[2:0]> Clock gear value CGSYSCR<GEAR[2:0]> 000 (fc) 0.82 ms 3.28 ms 13.11 ms 52.43 ms 209.72 ms 838.86 ms 100 (fc/2) 1.63 ms 6.55 ms 26.21 ms 104.86 ms 419.43 ms 1.68 s 101 (fc/4)
Page 456 Watchdog Timer(WDT) 21.2 Register TMPM3V6/M3V4 21.2.2 WDCR (Watchdog Timer Control Register) bit symbol After reset bit symbol After reset bit symbol After reset bit symbol WDCR After reset Bit Symbol Type Function 31-8 − Read as 0. WDCR Disable/Clear code 0xB1:Disable code 0x4E: Clear code Others:Reserved...
Page 457 TMPM3V6/M3V4 21.3 Operations 21.3.1 Basic Operation The Watchdog timer is consists of the binary counters that work using the system clock (fsys) as an input. Detecting time can be selected between 2 and 2 by the WDMOD<WDTP[2:0]>. The detect- ing time as specified is elapsed, the watchdog timer interrupt (INTWDT) generates, and the watchdog timer out pin (WDTOUT) output "Low".
Page 458 Watchdog Timer(WDT) 21.4 Operation when malfunction (runaway) is detected TMPM3V6/M3V4 21.4 Operation when malfunction (runaway) is detected 21.4.1 INTWDT interrupt generation In the Figure 21-2 shows the case that INTWDT interrupt generates (WDMOD<RESCR>="0"). When an overflow of the binary counter occurs, INTWDT interrupt generates. It is a factor of non-maska- ble interrupt (NMI).
Page 459 TMPM3V6/M3V4 21.4.2 Internal reset generation Figure 21-3 shows the internal reset generation (WDMOD<RESCR>="1"). MCU is reset by the overflow of the binary counter. In this case, reset status continues for 32 states. A clock is initialized so that input clock (fsys) is the same as a internal high-speed frequency clock (fosc). This means fsys = fosc.
Page 460 Watchdog Timer(WDT) 21.5 Control register TMPM3V6/M3V4 21.5 Control register The watchdog timer (WDT) is controlled by two control registers WDMOD and WDCR. 21.5.1 Watchdog Timer Mode Register (WDMOD) 1. Specifying the detection time of the watchdog timer <WDTP[2:0]>. Set the watchdog timer detecting time to WDMOD<WDTP[2:0]>. After reset, it is initialized to WDMOD<WDTP[2:0]>...
Page 461 TMPM3V6/M3V4 21.5.3 Setting example 21.5.3.1 Disabling control By writing the disable code (0xB1) to this WDCR register after setting WDMOD <WDTE> to "0," the watchdog timer can be disabled and the binary counter can be cleared. WDMOD ← − − −...
Page 462 Watchdog Timer(WDT) 21.5 Control register TMPM3V6/M3V4 Page 440 2019-02-06...
Page 463 TMPM3V6/M3V4 Flash Memory Operation This section describes the hardware configuration and operation of Flash memory. In this section, "1-word" means 32 bits. 22.1 Features 22.1.1 Memory Size and Configuration Table 22-1 and Figure 22-1 Figure 22-2show a built-in memory size and configuration of TMPM3V6/M3V4. Table 22-1 Memory size and configuration Block configuration Write time...
Page 464 Flash Memory Operation 22.1 Features TMPM3V6/M3V4 Flash memory configuration units ares described as "block" and "page". ・ Page One page is 32 words. Same address [31:7] is used in a page. First address of the group is [6:0] = 0 and the last address of the group is [6:0] = 0x7F. ・...
Page 465 TMPM3V6/M3V4 RESET selected by the level of the BOOT pin when reset is released Single chip mode Single boot mode Normal mode User boot mode Users determine a means for switching. On-board programming mode Figure 22-3 Mode transition Page 443 2019-02-06...
Page 466 Flash Memory Operation 22.1 Features TMPM3V6/M3V4 Single chip mode The single chip mode is a mode where the device can boot-up from Flash memory after reset. The mode contains two sub-modes in below. ・ Normal mode The mode where user application program is executed. ・...
Page 467 TMPM3V6/M3V4 22.1.4 Memory Map Figure 22-4 Figure 22-5 shows a comparison of the memory map in the single chip mode and single boot mode. In the single boot mode, built-in Flash memory is mapped to 0x3F80_0000 and subsequent addresses, and the built-in BOOT ROM is mapped to 0x0000_0000 through 0x0000_0FFF. Flash memory and RAM addresses are shown below.
Page 468 Flash Memory Operation 22.1 Features TMPM3V6/M3V4 0xFFFF_FFFF 0xFFFF_FFFF 0x3F80_FFFF Internal Flash ROM (64 KB) 0x3F80_0000 0x3F7F_FFFF Reserved 0x3F7F_F000 0x2000_1FFF 0x2000_1FFF Internal RAM Internal RAM (8 KB) (8 KB) 0x2000_0000 0x2000_0000 0x0000_FFFF 0x0000_0FFF Internal Flash ROM Internal BOOT ROM (64 KB) (4 KB) 0x0000_0000 0x0000_0000...
Page 469 TMPM3V6/M3V4 Note that when the system reset occurs, FCPMRA<BLKM[3:0]> is set to "1". The contents of the protect bit are maintained in the non-maskable state. FCPMRA<BLKM[3:0]> should be written as follows: Note: Use a 32-bit transfer instruction when the following writing operations, item1 and 2. 1.
Page 470 Flash Memory Operation 22.1 Features TMPM3V6/M3V4 22.1.6 Register 22.1.6.1 Register List Base Address = 0x41FF_F000 Register name Address(Base+) Security bit register FCSECBIT 0x0010 Flash Interface control register FCCR 0x001C Flash status register FCSR 0x0020 Flash protect status register A FCPSRA 0x0030 Flash protect mask register A FCPMRA...
Page 471 TMPM3V6/M3V4 22.1.6.3 FCCR (Flash Interface control register) bit symbol After reset bit symbol After reset bit symbol After reset bit symbol FLBOFF After reset Bit Symbol Type Function 31-1 − Read as "0". FLBOFF Control of Flash Interface with instruction Buffer (Note 1) 0: Enable Instruction Buffer 1: Disable Instruction Buffer (with Buffer clear ) This bit is a functional bit for controlling the Flash Interface .
Page 472 Flash Memory Operation 22.1 Features TMPM3V6/M3V4 22.1.6.4 FCSR (Flash status register) bit symbol After reset bit symbol After reset bit symbol After reset bit symbol RDY_BSY After reset Bit Symbol Type Function 31-1 − Read as "0". RDY_BSY Ready/Busy (Note 1) 0: Busy (during auto operation) 1: Ready (auto operation ends) This bit is a function bit to monitor flash memory from CPU.
Page 473 TMPM3V6/M3V4 22.1.6.5 FCPSRA (Flash protect status register) bit symbol After reset bit symbol After reset bit symbol After reset bit symbol BLK3 BLK2 BLK1 BLK0 After reset (Note 1) (Note 1) (Note 1) (Note 1) Bit Symbol Type Function 31-4 −...
Page 474 Flash Memory Operation 22.1 Features TMPM3V6/M3V4 Note 2: Do not modify FCPMRA<BLKM3> to <BLKM0> while data is being written/erased to/from the Flash memory. Note 3: When FCPMRA<BLKM3> to <BLKM0> are modified, read the register again to check whether the Flash is re- written.
Page 475 TMPM3V6/M3V4 22.2 Detail of Flash Memory In on-board programming, the CPU executes commands for reprogramming or erasing Flash memory. This reprog- ramming/erase control program should be prepared by the user beforehand. Since Flash memory content cannot be read while Flash memory is being written or erased, it is necessary to run the reprogram/erase control program on the built-in RAM.
Page 476 Flash Memory Operation 22.2 Detail of Flash Memory TMPM3V6/M3V4 For detail of the reset operation, refer to "Reset". After a given reset input, CPU will read the reset vector da- ta and then starts the routine after reset. 22.2.4 How to Execute Command The command execution is performed by writing command sequences to Flash memory with a store instruc- tion.
Page 477 TMPM3V6/M3V4 22.2.5.1 Automatic Page Program Operation Description The automatic page program writes data per page. When the program writes data to multiple pa- ges, a page command need to be executed in page by page. Writing across pages is not possible. Writing to Flash memory means that data cell of "1"...
Page 478 Flash Memory Operation 22.2 Detail of Flash Memory TMPM3V6/M3V4 22.2.5.3 Automatic Block Erase Operation Description The automatic erase command performs erase operation to the specified block. If the specified block is protected, erase operation is not executed. How to Set The 1st to 5th bus write cycles indicate the automatic block erase command.
Page 479 TMPM3V6/M3V4 In the security status, all addresses and all protect of Flash memory bits are erased. Confirm if da- ta and protect bits are erased normally. If necessary, execute the automatic protect bit erase, automat- ic chip erase or automatic block erase. All cases are the same as other commands, FCSR<RDY_BSY>...
Page 480 Flash Memory Operation 22.2 Detail of Flash Memory TMPM3V6/M3V4 22.2.6 Command Sequence 22.2.6.1 Command Sequence List Table 22-5 shows addresses and data of bus write cycle in each command. All command cycles except the 5th bus cycle of ID-Read command are bus write cycles. A bus write cy- cle is performed by 32-bit (1-word) data transfer instruction.
Page 481 TMPM3V6/M3V4 ・ PBA: Protect bit address (see Table 22-8) 22.2.6.2 Address Bit Configuration in the Bus Cycle Table 22-6 is used in conjunction with "Table 22-5 Command Sequence". Set the address setting according to the normal bus write cycle address configuration from the first bus cycle.
Page 482 Flash Memory Operation 22.2 Detail of Flash Memory TMPM3V6/M3V4 22.2.6.4 How to Specify Protect Bit (PBA) The protect bit is specified in 1-bit unit in programming and in 4-bit unit in erasing. Table 22-8 shows a protect bit selection table of the automatic protect bit program. The column of ad- dress example indicates an address described in upper side is used in the use boot mode and the lower side is used in the single boot mode.
Page 483 TMPM3V6/M3V4 22.2.6.6 Example of Command Sequence use boot mode Bus cycle Command Address 0x0000_0000 − − − − − − Read Data 0x0000_00F0 − − − − − − Address 0x0000_0550 0x0000_0AA0 0x0000_0550 − − − − Read/reset Data 0x0000_00AA 0x0000_0055 0x0000_00F0 −...
Page 484 Flash Memory Operation 22.2 Detail of Flash Memory TMPM3V6/M3V4 22.2.7 Flowchart 22.2.7.1 Automatic Program Start Automatic page programming command sequence (see the flowchart shown below) Address = Address + 0x80 The address of the last page? (set by a page) Automatic page programming Automatic Page Programming Command Sequence (Address/ Command) 0x0000_0054xx/0x0000_00AA...
Page 485 TMPM3V6/M3V4 22.2.7.2 Automatic Erase Start Automatic chip erase command sequence (see the flowchart shown below) Automatic chip erase completed Automatic chip erase command sequence Automatic block erase command sequence (address/ command) (address/ command) 0x0000_0550/0x0000_00AA 0x0000_0540/0x0000_00AA 0x0000_0AA0/0x0000_0055 0x0000_0AA0/0x0000_0055 0x0000_0550/0x0000_0080 0x0000_0550/0x0000_0080 0x0000_0550/0x0000_00AA 0x0000_0550/0x0000_00AA 0x0000_0AA0/0x0000_0055 0x0000_0AA0/0x0000_0055...
Page 486 Flash Memory Operation 22.3 How to Reprogram Flash using Single Boot Mode TMPM3V6/M3V4 22.3 How to Reprogram Flash using Single Boot Mode The single boot mode utilizes a program contained in built-in BOOT ROM for reprogramming Flash memory. In this mode, BOOT ROM is mapped to the area containing interrupt vector tables and Flash memory is mapped to another address area other than BOOT ROM area.
Page 487 TMPM3V6/M3V4 Table 22-10 Pin connection Interface UART Mode setting pin ο BOOT Reset pin ο RESET TXD0 ο (PE0) Communication RXD0 ο (PE1) ο:used ×:unused 22.3.3 Restrictions on Internal Memories Note that the single boot mode places restrictions on the built-in RAM and built-in flash memory as shown in Table 22-11.
Page 488 Flash Memory Operation 22.3 How to Reprogram Flash using Single Boot Mode TMPM3V6/M3V4 22.3.4.2 Flash Memory Chip Erase and Protect Bit Erase Flash memory chip erase and protect bit erase commands erase the entire blocks of Flash memory and write/erase protects of all blocks regardless of write/erase protect or security status. 22.3.5 Common Operation regardless of Command This section describes common operation under the boot program execution.
Page 489 TMPM3V6/M3V4 Start Initialize TMRB0 Prescaler is on.(source clock:φT0) High-to-low transition Point A on serial receive pin? TMRB0 starts counting up Low-to-high transition Point B on serial receive pin? Software-capture and save timer value (tAB) High-to-low transition Point C on serial receive pin? Software-capture and save timer value (tAC) Low-to-high transition Point D...
Page 490 Flash Memory Operation 22.3 How to Reprogram Flash using Single Boot Mode TMPM3V6/M3V4 Start tCD ← tAD > tCD? UART mode Not Connected Figure 22-10 Serial operation mode determination flowchart 22.3.5.2 Acknowledge Response Data The boot program represents processing states in specific codes and sends them to the controller. Table 22-13 to Table 22-16 show the values of acknowledge responses to each receive data.
Page 491 TMPM3V6/M3V4 Table 22-16 ACK response to Flash memory chip erase and protect bit erase operation Transmit data Description 0x54 Determined as a erase enable command 0x4F Erase command is complete. 0x4C Erase command is abnormally terminated. Note: Even when an erase command is performed normally, a Negative acknowledge may be returned by ACK response.
Page 492 Flash Memory Operation 22.3 How to Reprogram Flash using Single Boot Mode TMPM3V6/M3V4 Start Are all bytes the same? Are all bytes equal to FFH? Password area error Password area is normal. Figure 22-11 Password area check flowchart Password verification to Flash memory chip erase and protect bit erase command When a password is enable in the erase password necessity determination area as shown in Fig- ure 22-12 and the passwords are identical data, a password area error occurs.
Page 493 TMPM3V6/M3V4 To calculate the checksum for a series of 0xE5 and 0xF6, perform 8-bit addition. 0xE5 + 0xF6 = 0x1DB Take the two’s complement of the sum to the lower 8-bit, and that is a checksum value. So the boot pro- gram sends 0x25 to the controller.
Page 494 Flash Memory Operation 22.3 How to Reprogram Flash using Single Boot Mode TMPM3V6/M3V4 22.3.6 Transfer Format at RAM Transfer This section shows a RAM transfer command format. Transfer directions in the table are indicated as follows: Transfer direction (C→T): Controller to TMPM3V6/M3V4 Transfer direction (C←T): TMPM3V6/M3V4 to Controller Number of Transfer...
Page 495 TMPM3V6/M3V4 Number of Transfer transfer Transfer data Description direction bytes ACK response to CHECK SUM value First, checks if 5th to 17th byte of receive data have errors.(UART mode only) If re- ceive errors exist, sends a ACK response data 0x18 that means abnormal commu- Normal state: 0x10 nications and waits for a next operation command (3rd byte).
Page 496 Flash Memory Operation 22.3 How to Reprogram Flash using Single Boot Mode TMPM3V6/M3V4 22.3.7 Transfer Format of Flash memory Chip Erase and Protect Bit Erase This section shows a transfer format of Flash memory chip erase and protect bit erase commands. Transfer directions in the table are indicated as follows: Transfer direction (C→T): Controller to TMPM3V6/M3V4 Transfer direction (C←T): TMPM3V6/M3V4 to Controller...
Page 497 TMPM3V6/M3V4 Number of Transfer transfer Transfer data Description direction bytes ACK response to the CHECK SUM value If password necessity is set to "none", sends a normal ACK response data 0x40. Normal state: 0x40 If password necessity is set to "necessary", first checks if receive errors exist in the 5th byte to 17th byte receive data.
Page 498 Flash Memory Operation 22.3 How to Reprogram Flash using Single Boot Mode TMPM3V6/M3V4 22.3.8 Boot Program Whole Flowchart This section shows a boot program whole flowchart. Single Boot program starts Initialize Get SIO operation mode SIO operation mode? UART Cannot be set Baud rate setting ? Can be set...
Page 499 TMPM3V6/M3V4 22.3.9 Reprogramming Procedure of Flash using reprogramming algorithm in the on- chip BOOT ROM This section describes the reprogramming procedure of the flash using reprogramming algorithm in the on- chip boot ROM. 22.3.9.1 Step-1 The condition of Flash memory does not care whether a user program made of former versions has been written or erased.
Page 500 Flash Memory Operation 22.3 How to Reprogram Flash using Single Boot Mode TMPM3V6/M3V4 22.3.9.3 Step-3 If the password verification is complete, the boot program transfer a programming routine (a) from the host into the on-chip RAM. The programming routine must be stored in the range from 0x2000_0400 to the end address of RAM.
Page 501 TMPM3V6/M3V4 22.3.9.5 Step-5 The boot program executes the programming routine (a) to download new application program codes from the host and programs it into the erased flash area. When the programming is complete, the writing or erase protection of that flash area in the user’s program must be set. In the example below, new program code comes from the same host via the same SIO0/UART0/ chan- nel as for the programming routine.
Page 502 Flash Memory Operation 22.4 Programming in the User Boot Mode TMPM3V6/M3V4 22.4 Programming in the User Boot Mode A user Boot mode is to use flash memory programming routine defined by users. It is used when the data trans- fer buses for flash memory program code on the user application is different from the serial I/O. It operates in the single chip mode;...
Page 503 TMPM3V6/M3V4 22.4.1.2 Step-2 This section explains the case that a programming routine storied in the reset routine. First, the reset rou- tine determines to enter the user boot mode. If mode switching conditions are met, the device enters the user boot mode to reprogram data. New Application (Host) Program Code...
Page 504 Flash Memory Operation 22.4 Programming in the User Boot Mode TMPM3V6/M3V4 22.4.1.4 Step-4 Jump to the reprogramming routine in the built-in RAM to release the write/erase protection for the old application program, and to erase a flash in block unit. (Host) New Application Program Code...
Page 505 TMPM3V6/M3V4 22.4.1.6 Step-6 Set RESET to "0". Upon reset, Flash memory is set to the normal mode. After reset, the CPU will start along with the new application program. (Host) TMPM3V6/M3V4 (I/O) 0 → 1 RESET Flash memory New application program code Set to normal mode [Reset procedure]...
Page 506 Flash Memory Operation 22.4 Programming in the User Boot Mode TMPM3V6/M3V4 22.4.2 (1-B) Procedure that a Programming Routine is transferred from External Host 22.4.2.1 Step-1 A user determines the conditions (e.g., pin status) to enter the user boot mode and the I/O bus to be used to transfer data.
Page 507 TMPM3V6/M3V4 22.4.2.2 Step-2 This section explains the case that a programming routine storied in the reset routine. First, the reset rou- tine determines to enter the user boot mode. If mode switching conditions are met, the device enters the user boot mode to reprogram data. New application (Host) program code...
Page 508 Flash Memory Operation 22.4 Programming in the User Boot Mode TMPM3V6/M3V4 22.4.2.4 Step-4 Jump to the reprogramming routine in the built-in RAM to release the write/erase protection for the old application program, and to erase a flash in block unit. (Host) New application program code...
Page 509 TMPM3V6/M3V4 22.4.2.6 Step-6 Set RESET to "0". Upon reset, Flash memory is set to the normal mode. After reset, the CPU will start along with the new application program. (Host) TMPM3V6/M3V4 (I/O) 0 → 1 RESET Flash memory New application program code Set to normal mode [Reset procedure]...
Page 510 Flash Memory Operation 22.4 Programming in the User Boot Mode TMPM3V6/M3V4 Page 488 2019-02-06...
Page 511 TMPM3V6/M3V4 23. Debug Interface 23.1 Specification Overview TMPM3V6/M3V4 contains the Serial Wire JTAG Debug Port (SWJ-DP) unit for interfacing with the debugging tools and the Embedded Trace Macrocell™(ETM) unit for instruction trace output.Trace data is output to the dedi- cated pins(TRACEDATA[1:0], SWV) for the debugging via the on-chip Trace Port Interface Unit (TPIU). For details about SWJ-DP, ETM and TPIU, refer to the Arm manual "Cortex-M3 Technical Reference Manual"...
Page 512 Debug Interface 23.4 Pin Functions TMPM3V6/M3V4 23.4 Pin Functions The debug interface pins can also be used as general-purpose ports. The PB3 and PB4 pins are shared between the JTAG debug port function and the Serial Wire Debug Port func- tion.
Page 513 TMPM3V6/M3V4 23.5 Peripheral Functions in Halt Mode When the Cortex-M3 core enters in the halt mode, the watchdog-timer (WDT) automatically stops. Other periph- eral functions continue to operate. Page 491 2019-02-06...
Page 514 Debug Interface 23.6 Connection with a Debug Tool TMPM3V6/M3V4 23.6 Connection with a Debug Tool 23.6.1 About connection with debug tool Concerning a connection with debug tools, refer to manufactures recommendations. Debug interface pins contain a pull-up resistor and a pull-down resistor.When debug interface pins are con- nected with external pull-up or pull-down, please pay attention to input level.
Page 515 TMPM3V6/M3V4 24. Port Section Equivalent Circuit Schematic Basically, the gate symbols written are the same as those used for the standard CMOS logic IC [74HCXX] series. The input protection resistance ranges from several tens of Ω to several hundred Ω. Feedback resistor and Damp- ing resistor are shown with a typical value.
Page 516 Port Section Equivalent Circuit Schematic 24.3 TMPM3V6/M3V4 24.3 Output Data P-ch Open-drain Enable N-ch Output Enable I/O port BOOT Schmitt Programmable Input Enable Pull-up Resistor Pull-up Enable Pull-down Enable Programmable Pull-down Resistor 24.4 PM0 to 1, PP0 to 1 Input AIN Output Data P-ch Open-drain Enable...
Page 517 TMPM3V6/M3V4 24.5 X1, X2 Clock Oscillator Circuit 1kΩ (typ.) 500kΩ (typ.) High-frequency Oscillation Enable 24.6 XT1, XT2 Clock Oscillator Circuit 120kΩ (typ.) 20MΩ (typ.) Low-frequency Oscillation Enable 24.7 RESET Pull-up Resistor Reset Input Port Schmitt 24.8 MODE MODE Input Port Schmitt (Note)MODE pin is fixed to GND.
Page 518 Port Section Equivalent Circuit Schematic 24.9 FTEST3 TMPM3V6/M3V4 24.9 FTEST3 FTEST3 Open (Note)FTEST3 pin is fixed to Open. 24.10 VREFH, VREFL AVDD AVDD5(VREFH) VREFH String Resistor VREFL AVSS(VREFL) AVSS Page 496 2019-02-06...
Page 519 TMPM3V6/M3V4 Electrical Characteristics 25.1 Absolute Maximum Ratings Parameter Symbol Rating Unit DVDD5 −0.3 to 6.0 Supply voltage RVDD5 −0.3 to 6.0 AVDD5 −0.3 to 6.0 Input voltage −0.3 to VDD + 0.3 Per pin Low-level output current ΣI Total Per pin −5 High-level output current...
Page 520 Electrical Characteristics 25.2 DC Electrical Characteristics (1/3) TMPM3V6/M3V4 25.2 DC Electrical Characteristics (1/3) DVDD5 = RVDD5 = AVDD5 = 3.9V to 5.5V , DVSS = AVSS = 0V, Ta = −40 to 85 °C Parameter Symbol Condition Typ. (Note 1) Unit = 8 to 10 MHz DVDD5...
Page 521 TMPM3V6/M3V4 25.3 DC Electrical Characteristics (2/3) DVDD5 = RVDD5 = AVDD5 = 3.9V to 5.5V , DVSS = AVSS = 0V, Ta = −40 to 85 °C Parameter Symbol Condition Typ. (Note 1) Unit Per pin − − Per group 3.9 V ≤...
Page 522 Electrical Characteristics 25.4 DC Electrical Characteristics (3/3) TMPM3V6/M3V4 25.4 DC Electrical Characteristics (3/3) DVDD5 = RVDD5 = AVDD5 = 3.9V to 5.5V , DVSS = AVSS = 0V, Ta = −40 to 85 °C Parameter Symbol Condition Typ. (Note 1) Unit NORMAL (Note 2) −...
Page 523 TMPM3V6/M3V4 25.5 12/10-bit AD Converter Electrical Characteristics DVDD5 = RVDD5 = 4.5V to 5.5V , DVSS = AVSS = 0V, Ta = −40 to 85 °C Parameter Symbol Condition Typ. Unit Analog reference voltage (+) DVDD5 AVDD5 = V AVDD5 −...
Page 524 Electrical Characteristics 25.6 AC Electrical Characteristics TMPM3V6/M3V4 25.6 AC Electrical Characteristics 25.6.1 AC Measurement Condition The AC characteristics data of this chapter is measured under the following conditions unless otherwise no- ted. ・ Output levels: High = 0.8 × DVDD5, Low = 0.2 × DVDD5 ・...
Page 525 TMPM3V6/M3V4 SCLK Output Mode Equation 40 MHz Parameter Symbol Unit SCLK cycle (programmable) − − /2 − 20 Output Data ← SCLK rise − − SCLK rise → Output Data hold /2 − 20 − − Valid Data Input ← SCLK rise −...
Page 526 Electrical Characteristics 25.6 AC Electrical Characteristics TMPM3V6/M3V4 25.6.3 Serial Bus Interface (I2C/SIO) 25.6.3.1 I2C Mode In the table below, the letter x represents the I2C/SIO operation clock cycle time which is identical to the fsys cycle time. It varies depending on the programming of the clock gear function.It varies depend- ing on the programming of the clock gear function.
Page 527 TMPM3V6/M3V4 25.6.3.2 Clock-Synchronous 8-bit SIO mode In the table below, the letter x represents the I2C/SIO operation clock cycle time which is identical to the fsys cycle time. It varies depending on the programming of the clock gear function. SCK input mode (for an SCK signal with a 50% duty cycle) [Input] Equation 40 MHz...
Page 528 Electrical Characteristics 25.6 AC Electrical Characteristics TMPM3V6/M3V4 SCK output mode (for an SCK signal with a 50% duty cycle) Equation 40 MHz Parameter Symbol Unit SCK cycle (programmable) 16x (Note1) − − /2 − 20 (Note2) Output Data ← SCK rise −...
Page 529 TMPM3V6/M3V4 25.6.4 Synchronous Serial Interface (SSP) 25.6.4.1 AC Measurement Condition The letter "T" used in the equations in the table represents the period of the input clock (f ) into PCLK the internal prescaler. ・ Output levels : High = 0.7 × DVDD5, Low = 0.3 × DVDD5 ・...
Page 530 Electrical Characteristics 25.6 AC Electrical Characteristics TMPM3V6/M3V4 Note: Baud rate clock is set under below condition: ・ Master mode: m = (<CPSDVSR> × (1 + <SCR>)) = fsys/SPCLK <CPSDVSR>is set only even number and "m" must set between the range of 65024 ≥ m ≥ 2 . ・...
Page 531 TMPM3V6/M3V4 25.6.4.2 SSP SPI mode (Master) ・ fsys ≥ 2 × SPxCLK (Maximum) ・ fsys ≥ 65024 × SPxCLK (Minimum) (1) Master SSPCR0<SPH>="0" (Data is latched on the first edge.) OFSM SPCLK output (Master) Internal (SSPCR0<SPO>=0) Clock state Internal SPCLK output (Master) Clock state (SSPCR0<SPO>=1) ODSM...
Page 532 Electrical Characteristics 25.6 AC Electrical Characteristics TMPM3V6/M3V4 25.6.4.3 SSP SPI mode (Slave) ・ fsys ≥ 12 × SPCLK (Maximum) ・ fsys ≥ 65024 × SPCLK (Minimum) (3) Slave SSPCR0<SPH>="0" (Data is latched on the first edge.) OFSS SPCLK input (SSPCR0<SPO>=0) SPCLK input (SSPCR0<SPO>=1) IDSS...
Page 533 TMPM3V6/M3V4 25.6.5 Event Counter In the table below, the letter x represents the TMRB operation clock cycle time which is identical to the fsys cycle time. It varies depending on the programming of the clock gear function. Equation 40 MHz Parameter Symbol Unit...
Page 534 Electrical Characteristics 25.6 AC Electrical Characteristics TMPM3V6/M3V4 25.6.8 SCOUT pin AC Characteristics Equation 40 MHz Parameter Symbol Unit High-level pulse width 0.5T − 5 − − Low-level pulse width 0.5T − 5 − − Note: In the above table, the letter T represents the cycle time of the SCOUT output clock. SCOUT Page 512 2019-02-06...
Page 535 TMPM3V6/M3V4 25.6.9 Debug Communication 25.6.9.1 SWD Interface Parameter Symbol Unit CLK cycle − CLK rise → Output data hold − CLK rise → Output data valid − Input data valid ← CLK rise − CLK rise → Input data hold −...
Page 536 Electrical Characteristics 25.6 AC Electrical Characteristics TMPM3V6/M3V4 25.6.10 ETM Trace ・ Output levels: High = 0.7 × DVDD5, Low = 0.3 × DVDD5 ・ Load capacitance: TRACECLK = 25pF, TRACEDATA = 20pF Parameter Symbol Unit TRACECLK cycle − tclk TRACEDATA valid ← TRACECLK rise −...
Page 537 TMPM3V6/M3V4 25.7 Recommended Oscillation Circuit Figure 25-1 High-frequency oscillation connection Figure 25-2 Low-frequency oscillation connection Note: To obtain a stable oscillation, load capacity and the position of the oscillator must be configured properly. Since these factors are strongly affected by substrate patterns, please evaluate oscillation stability using the substrate you use.
Page 538 Electrical Characteristics 25.7 Recommended Oscillation Circuit TMPM3V6/M3V4 Page 516 2019-02-06...
Page 539 TMPM3V6/M3V4 26. Package Dimensions 26.1 TMPM3V6FWFG Type:LQFP100-P-1414-0.50H Page 517 2019-02-06...
Page 540 Package Dimensions 26.2 TMPM3V6FWDFG TMPM3V6/M3V4 26.2 TMPM3V6FWDFG Type:QFP100-P-1420-0.65A Unit: mm Page 518 2019-02-06...
Page 541 TMPM3V6/M3V4 26.3 TMPM3V4FWUG/TMPM3V4FSUG Type:LQFP64-P-1010-0.50E Page 519 2019-02-06...
Page 542 Package Dimensions 26.4 TMPM3V4FWEFG/TMPM3V4FSEFG TMPM3V6/M3V4 26.4 TMPM3V4FWEFG/TMPM3V4FSEFG Type:QFP64-P-1414-0.80A Unit: mm Page 520 2019-02-06...
Page 543 • The information contained herein is presented only as guidance for Product use. No responsibility is assumed by TOSHIBA for any infringement of patents or any other intellectual property rights of third parties that may result from the use of Product. No license to any intellectual property right is granted by this document, whether express or implied, by estoppel or otherwise.

This manual is also suitable for:

Tmpm3v6 Tmpm3v4

Toshiba TX03 Series Manual

Tmpm3V6/M3V4

2 Product Information

3 Processor Core

4 Memory Map

5 Reset Operation

6 Clock/Mode Control

Quick Links

Related Manuals for Toshiba TX03 Series

Summary of Contents for Toshiba TX03 Series

This manual is also suitable for:

Table of Contents