Control Input - HP 8112A Operating, Programming And Servicing Manual
50 mhz programmable pulse generator
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- Operating, programming and servicing manual (112 pages) ,
- Operating, programming and servicing manual (406 pages)
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Address Decoder
Mode and Range
Decoders
Control Input Circuits
Timing IC
1 0.3-2 Servicing the Timing and
Slope Generators
An eight line decoder U lOO is controlled by address lines LA3 to LA5
with WS 1 . The decoder output lines determine which timing, mode
or range circuit latches data from the data bus
shown in Table 10.3- 1. The address decoder also controls the output
of the contents of the error latches onto the data bus.
Table 1 0.3-1. Address decoder enable outputs
UlOO pin
Mnemonic
SRC
7
PIC
10
11
CLR
MAMO
12
WIC
13
14
DIC
Under the control of the Address Decoder, these decoders latch data
from the data bus and input it to the various switches that select
control and trigger modes and the switching transistors which select
the range capacitor to be used by the slope IC .
Refer to Figure 10.3-4. The control input signal is clamped within
±5 V by the protection diodes CR130 to CR132. For Period , Delay,
and Width control the input voltage is rectified by precision rectifi e r
U132B and associated components. The signal then passes to the
control mode selector switch U130 where microprocessor control
signals ACO and ACl from the mode decoder UlOl select its route to
the appropriate timing IC.
When the High Level Control
signal is routed through the switch
with associated components
10.5. The low pass filter is needed because of the 20 µs settling time
inherant in HILC mode operation.
The timing ICs used in the HP 8 1 12A are programmable timers
which can be used to produce repetition rates, pulse widths and
delay times by utilizing a variety of trigger and gate mode inputs.
(
LDO to LD7
IC
Circuit Action
Load Range Decoder
U300
Load Period Generator
U200
Output Error Latches
U 142
Load Mode Decoder
U l O l
Load Width Generator
U240
Load Delay Generator
U220
(
)
HILC
is selected, the control input
(
)
U131
and low pass fi l ter
)
, to the output stages. See chapter
)
as
(
U1 32a
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