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Scheme Logic
Figures 2.9.1.2 (a) and 2.9.1.3 (a) show the scheme logic of the OVS1 and OVG1 overvoltage
protection with selective definite time or inverse time characteristic.
The definite time protection is selected by setting [OV∗1EN] to "DT", and trip signal
OV∗1_TRIP is given through the delayed pick-up timer TO∗1. The inverse time protection is
selected by setting [OV∗1EN] to "IDMT", and trip signal OV∗1_TRIP is given.
The OVS1 and OVG1 protections can be disabled by the scheme switch [OV∗1EN] or the PLC
signal OV∗1_BLOCK.
These protections are available to trip instantaneously by the PLC signal OV∗1_INST_TP
except for [OV∗1EN]= "OFF" setting.
Figures 2.9.1.2 (b) and 2.9.1.3 (b) show the scheme logic of the OVS2 and OVG2 protection
with definite time characteristic. The OV∗2 gives the signal OV∗2_ALARM through delayed
pick-up timer TO∗2.
The OV∗2_ALARM can be blocked by incorporated scheme switch [OV∗2EN] and the binary
input signal OV∗2_BLOCK.
These protections are also available to alarm instantaneously by the PLC signal
OV∗2_INST_TP.
Overvoltage Inverse Time
Curves
1000.000
100.000
10.000
1.000
0.100
1
1.5
2
Applied Voltage (x Vs)
Figure 2.9.1.1 IDMT Characteristic
94
TMS = 10
TMS = 5
TMS = 2
TMS = 1
2.5
3
6 F 2 S 0 8 5 0
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