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Frame
1
Ia
1 Ia
header
10 bits
8
1 4
(1)
Frame
V1
No.
V.COM1
V.COM2
V.COM3
0
1
2
3
4
V1 /
V1 /
V1 /
5
SPARE
SPARE
SPARE
6
7
8
9
10
11
Legend
Ia, Ib, Ic :
Phase current
V1 :
Positive-sequence voltage
Io :
Zero-sequence current
ON / OFF :
Control data
RDY :
Ready
SA :
Sampling address for a cycle
SSA
Sampling address for a second
SP :
Sampling synchronization
CRC :
Cyclic redundancy check
S.F.C.
Simultaneous fault control
(synchronized test trigger signal)
Figure N-2 Data Transmission Format of B-MODE and GPS-MODE
User configurable commands are as:
COM1 to COM3:
COM4 and COM5:
SUB_COM:
V.COM1 to V.COM3 and S.V.COM1 to S.V.COM12: If the OST and FL functions are not used,
I.COM1 to I.COM3 and S.I.COM1 to S.I.COM12: If the DIFG function is not used, the user can
88 bits
Ib 1
Ib
1
Ic
4 1
8
1
8
(2)
COM1
SA
I.COM1
I.COM2
S.V.COM∗
1
V1 / SPARE
2
V1 / SPARE
3
V1 / SPARE
4
V1 / SPARE
5
V1 / SPARE
Io /
Io /
6
V1 / SPARE
SPARE
SPARE
7
V1 / SPARE
8
V1 / SPARE
9
V1 / SPARE
10
V1 / SPARE
11
V1 / SPARE
12
V1 / SPARE
Used for sampling address.
Used for transfer signals.
These commands are sent every 12 frames. SUB_COM1 and SUB_COM2
are assigned to ARC_BLOCK and Local test signals as default setting. If
these signals are changed, the related functions cannot be applied.
the user can use these commands. The V.COM1 to V.COM3 commands
are sent every frame. The S.V.COM1 to S.V.COM12 are sent every 12
frames.
use these commands. The I.COM1 to I.COM3 commands are sent every
frame. The S.I.COM1 to S.I.COM12 are sent every 12 frames.
421
1 Ic
V1 1 Io
87
8
SA/
5
S
SSA
1
1 4
4 1 4
3 1 1 1 1 1 1 1 1 2 1
COM2
COM3
COM4
SA
SSA
85S1
Io
SUB2-COM∗
CBDS / RA
I.COM3
∗
S.I.COM∗
1
Io / SPARE
1
RA0 / CBDS-A
2
Io / SPARE
2
RA1 / CBDS-B
3
Io / SPARE
3
RA2 / CBDS-C
4
Io / SPARE
4
RA0 / CBDS-A
Io /
5
Io / SPARE
5
RA1 / CBDS-B
SPARE
6
Io / SPARE
6
RA2 / CBDS-C
7
Io / SPARE
7
RA0 / CBDS-A
8
Io / SPARE
8
RA1 / CBDS-B
9
Io / SPARE
9
RA2 / CBDS-C
10
Io / SPARE
10
RA0 / CBDS-A
11
Io / SPARE
11
RA1 / CBDS-B
12
Io / SPARE
12
RA2 / CBDS-C
(*) Time data are transmitted once per two cycle.
6 F 2 S 0 8 5 0
1
8
R
R
S
S
R
C
1
CRC
5
A
D
P
A
A
R
S
1
Y
2
C
2
8
Fixed
SUB2
R
COM5
bit
COM
D
Y
85S2
SA
SP1
SUB-COM∗
∗
0
8
0
2
, 2
1
9
0
2
, 2
2
10
0
2
, 2
3
11
0
2
, 2
1
SP flag
4
12
1
ARC BLOCK
2
, 2
5
13
2
Local test
2
, 2
6
14
3
0
2
, 2
7
15
1
2
, 2
5
-
4
-
S.F.C.
-
Time
(3)
data(*)
Next
Frame
1 CRC
1
6
(5)
S
S
SUB3
A
P
COM
1
RA2
SUB3_COM∗
RA2
∗
1
RA3 / SPARE
2
RA4 / SPARE
3
RA5 / SPARE
4
RA3 / SPARE
5
RA4 / SPARE
6
RA5 / SPARE
7
RA3 / SPARE
8
RA4 / SPARE
9
RA5 / SPARE
10
RA3 / SPARE
11
RA1 / SPARE
12
RA2 / SPARE
(4)
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