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1.1.5 Enhanced Addressing Modes
Addressing in the CPU32 is register oriented. Most instructions allow the results of the
specified operation to be placed either in a register or in memory. There is no need for
extra instructions to store register contents in memory.
There are seven basic addressing modes:
1. Register Direct
2. Register Indirect
3. Register Indirect with Index
4. Program Counter Indirect with Displacement
5. Program Counter Indirect with Index
6. Absolute
7. Immediate
The register indirect addressing modes include postincrement, predecrement, and off-
set capability. The PC relative mode also has index and offset capabilities. In addition
to the addressing modes, many instructions implicitly specify the use of a status reg-
ister, SP, and/or PC. Addressing is explained fully in SECTION 3 DATA ORGANIZA-
TION AND ADDRESSING CAPABILITIES. A summary of M68000 Family addressing
modes is found in APPENDIX A M68000 FAMILY SUMMARY.
1.1.6 Instruction Set
The instruction set of the CPU32 is very similar to that of the MC68020 (see Table 1-
1). Two new instructions have been added to facilitate controller applications — low-
power stop (LPSTOP) and table lookup and interpolate (TBL). The following M68020
instructions are not implemented on the CPU32:
BFxxx — Bit Field Instructions (BFCHG, BFCLR, BFEXTS, BFEXTU, BFFFO
CALLM, RTM — Call Module, Return Module
CAS, CAS2 — Compare and Set (Read-Modify-Write Instructions)
cpxxx Coprocessor Instructions (cpBcc, cpDBcc, cpGEN, cp RESTORE,
PACK, UNPK Pack, Unpack BCD Instructions
The CPU32 traps on unimplemented instructions and illegal effective addressing
modes, allowing the user to emulate instructions or to define special-purpose func-
tions. However, Motorola reserves the right to use all currently uniplemented instruc-
tions operation codes for future M68000 core enhancements.
See SECTION 4 INSTRUCTION SET for comprehensive information.
1.1.6.1 Table Lookup and Interpolation Instructions
To speed up real-time applications, a range of discrete data points is often precalcu-
lated from a continuous control function, then stored in memory. A full range of data
can require an inordinate amount of memory. The table instructions make it possible
MOTOROLA
1-4
BFINS, BFSET, BFTST)
cpSAVE, cpScc, cpTRAPcc)
OVERVIEW
CPU32
REFERENCE MANUAL
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