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DIVS
DIVSL
Condition Codes:
X
N
Z
—
*
*
X
Not affected.
N
Set if quotient is negative. Cleared otherwise. Undefined if overflow or divide
by zero occurs.
Z
Set if quotient is zero. Cleared otherwise. Undefined if overflow or divide by
zero occurs.
V
Set if division overflow occurs; undefined if divide by zero occurs. Cleared oth-
erwise.
C
Always cleared.
Instruction Format (word form):
15
14
13
1
0
0
Instruction Fields:
Register field — Specifies any of the eight data registers. This field always specifies
the destination operand.
Effective Address field — Specifies the source operand. Only data addressing modes
are allowed as shown:
Addressing Mode
Dn
An
(An)
(An) +
– (An)
(d
, An)
16
(d
, An, Xn)
8
(bd, An, Xn)
Overflow occurs if the quotient is larger than a 16-bit signed integer.
CPU32
REFERENCE MANUAL
Signed Divide
V
C
*
0
12
11
10
9
0
REGISTER
Mode
Register
000
Reg. number: Dn
—
—
010
Reg. number: An
011
Reg. number: An
100
Reg. number: An
101
Reg. number: An
110
Reg. number: An
110
Reg. number: An
INSTRUCTION SET
8
7
6
5
1
1
1
Addressing Mode
(xxx).W
(xxx).L
#〈data〉
(d
, PC)
16
(d
, PC, Xn)
8
(bd, PC, Xn)
NOTE
DIVS
DIVSL
4
3
2
1
EFFECTIVE ADDRESS
MODE
REGISTER
Mode
Register
111
000
111
001
111
100
111
010
111
011
111
011
MOTOROLA
0
4-67
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