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• DMAC GA Signal Table (3/7)
No.
Signal Name
46
IORDX
47
IOWRX
48
DMADE
50
PCIDAK
51
DSCDAK
52
PTCDAX
53-55
CD0-2AKX
56
C5A0
57
LASTO
58
TXD
59
RTS
62
RXD
63
CTS
64, 65
FIFOC1, 0
66
PCIDRQ
67
DSCDREQ
I: Input
O: Output
DP120F/DP125F Circuit Description
Type
O
I/O read signal (active-low)
Reads data into each IC and I/O.
O
I/O write signal (active-low)
Writes data to each IC and I/O.
O
DMA data enable (active-low)
Indicates to the PTC GA (IC45) that DMA transfer is
to be performed.
O
PC interface DMA acknowledge signal (active-low)
Indicates to the PTC GA that DMA transfer is to be
performed with the PC interface.
O
DSC DMA acknowledge signal (active-low)
Indicates to the PTC GA that DMA transfer is to be
performed with the DSC (IC59).
O
PTC DMA acknowledge signal (active-low)
Indicates to the PTC GA that DMA transfer is to be
performed.
O
CODEC DMA acknowledge 0-2 signals (active-low)
Indicates to the PTC GA that DMA transfer is to be
performed with the CODEC (IC51).
O
PIX DMA CH5 A0 signal
A0 of CH5 for PIX DMA transfer.
O
PIX DMA CH5 last byte signal
Last transfer flag of CH5 for PIX DMA transfer.
O
UART transmit data
Transmit data to be output to the GA-1020 (PCL
PBA).
-
Unused
I
Receive data to be input from the GA-1020.
-
Signal ground (Pull down)
I
FIFO count 0 and 1 signals
The count data of the words to be transferred in DMA
mode is input from the PTC GA.
I
PC interface DMA request signal (active-low)
The PTC GA makes a request for DMA transfer with
the PC interface.
I
DSC DMA request signal (active-low)
The PTC GA makes a request for DMA transfer with
the DSC.
I/O: Bidirectional
Functions
7-56
March 2000 © TOSHIBA TEC
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