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22 HW Processor (HWP) and Sound Output (SDAC2)
22.5 Interrupts
The HWP has a function to generate the interrupts shown in Table 22.5.1.
Interrupt
Interrupt flag
Error occurrence HWPINTF.HWP1IF When a sound play error (see Table 22.4.1.2) or a memory
State transition HWPINTF.HWP0IF When a state transition of which the interrupt has not been
Interrupt enable
To enable HWP interrupts, the HWPINTE.HWPIE bit must be set to 1. An interrupt request is sent to the CPU
only when the interrupt flag is set in this status. For more information on interrupt control, refer to the "Interrupt"
chapter.
State transition interrupt mask
The HWP provides a HWP internal register that contains the interrupt mask bits used for setting whether to set
the HWPINTF.HWP0IF bit (to generate an interrupt) or not when a state transition occurs. By setting the inter-
rupt mask bits to 0, an interrupt can be generated when the corresponding state transition occurs.
Function
Interrupt mask bit
Sound Play
INTMASK.TO_MUTE
INTMASK.TO_PAUSE
INTMASK.TO_PLAY
INTMASK.TO_IDLE
Memory Check INTMASK.TO_PROCESSING mc_state_idle state → mc_state_ram_rw, ram_march_c, checksum, crc state
INTMASK.TO_IDLE
22.6 HWP Internal Registers
The HWP internal registers are switched to the Sound Play function registers or the Memory Check function reg-
isters according to the set value of the FUNCTION.ID[7:0] bits when the HWPCTL.HWPEN bit is set to 1. Table
22.6.1 lists the HWP internal register map.
Address
Base + 0x00
FUNCTION
Base + 0x02
INTMASK
Base + 0x04
ROMADDR
Base + 0x08
ROMSIZE
Base + 0x0c
KEYCODE
Base + 0x10
COMMAND_0 Ch.0 Command Register
Base + 0x12
COMMAND_1 Ch.1 Command Register
Base + 0x14
SENTENCE_0 Ch.0 Sentence Number Setting Register
Base + 0x16
SENTENCE_1 Ch.1 Sentence Number Setting Register
Base + 0x18
VOLUME_0
Base + 0x1a
VOLUME_1
Base + 0x1c
REPEAT_0
Base + 0x1e
REPEAT_1
Base + 0x20
SPEED_0
Base + 0x24
PITCH_0
Base + 0x40
STATE_0
Base + 0x42
STATE_1
Base + 0x44
ERROR
Base + 0x46
STATUS
Base + 0x48
–
Base + 0x4c
VERSION
22-18
Table 22.5.1 HWP Interrupt Function
check error (see Table 22.4.2.2) has occurred
masked occurs
Table 22.5.2 State Transition Interrupt Mask Bits
sp_state_play state → sp_state_mute state
sp_state_play state → sp_state_pause state
sp_state_idle, mute, pause state → sp_state_play state
sp_state_init, mute, pause, play state → sp_state_idle state
mc_state_init, mc_state_ram_rw, ram_march_c, checksum, crc state → mc_state_
idle state
Table 22.6.1 HWP Internal Register Map
Sound Play function
Function ID Register
Interrupt Mask Register
ROM Address Register
ROM Size Register
Key Code Register
Ch.0 Volume Control Register
Ch.1 Volume Control Register
Ch.0 Repeat Control Register
Ch.1 Repeat Control Register
Ch.0 Playback Speed Conversion Register –
Ch.0 Playback Pitch Conversion Register
Ch.0 State Monitor Register
Ch.1 State Monitor Register
Error Status Register
Operating Status Register
–
Version Number Register
Seiko Epson Corporation
Set condition
State transition
Register name
Memory Check function
FUNCTION
Function ID Register
INTMASK
Interrupt Mask Register
MEMADDR
Memory Address Register
MEMSIZE
Memory Size Register
INITVALUE
Initial Value Setting Register
COMMAND
Command Register
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
STATE
State Monitor Register
–
–
ERROR
Error Status Register
STATUS
Operating Status Register
RESULT
Calculation Result Register
VERSION
Version Number Register
Clear condition
Writing 0.
Writing 0.
Base = 0x00156700
S1C31D41 TECHNICAL MANUAL
(Rev. 1.1)
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