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Transition takes place automatically by the
initial boot sequence after a request from
the reset source is canceled.
OSC1
HALT
OSC1
RUN
Figure 2.4.2.1 Operating Mode-to-Mode State Transition Diagram
Canceling HALT or SLEEP mode
The conditions listed below generate the HALT/SLEEP cancelation signal to cancel HALT or SLEEP mode and
put the CPU into RUN mode.
• Interrupt request from a peripheral circuit
• NMI from the watchdog timer
• Reset request
S1C31D41 TECHNICAL MANUAL
(Rev. 1.1)
RESET
(Initial state)
IOSC
RUN
CLGSCLK.CLKSRC[1:0] = 0x3
OSC3
RUN
OSC3
HALT
Seiko Epson Corporation
2 POWER SUPPLY, RESET, AND CLOCKS
IOSC
HALT
CLGSCLK.CLKSRC[1:0] = 0x1
EXOSC
∗ In RUN and HALT modes, the clock sources not used
as SYSCLK can be all disabled.
WFI/WFE instruction
(SLEEPDEEP = 1)
RUN
SLEEP
HALT/SLEEP
cancelation signal
(wake-up)
RUN
EXOSC
HALT
2-15
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