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Chapter 6. Service Request Function
6.33.3
Erase Cycles
The flash component on the PACSystems CPU is rated for 100K erase cycles. Erase cycles occur
under the following conditions:
▪
Write to flash is commanded from the programmer.
▪
Clear flash operation.
▪
Flash compaction after a power cycle when flash memory allotted for SVC_REQ 57 has become
full.
6.33.4
Discrete Memory
Discrete memory can be written to as individual bits or as bytes. For more information, see Address.
Force and transition information is not written to nonvolatile storage.
6.33.5
Retentiveness
Writing values to nonvolatile storage for non-retentive memory such as %T does not make the
memory retentive. For example, all values stored to %T memory are set to zero on power-up or a
STOP Mode to RUN Mode transition. You can, however, read such values from storage after power-
up or STOP Mode to RUN Mode transition by using SVC_REQ 56.
6.33.6
Maximum of One Active Instruction
When SVC_REQ 57 is active, it does not support an interrupt that attempts to activate SVC_REQ 56
or a second instance of SVC_REQ 57.
6.33.7
Storage Disabled Conditions
By default, the following write operations disable SVC_REQ 57 until logic is written to nonvolatile
storage:
▪
RUN Mode Store (RMS), even if a second RMS reverts everything to the original state
▪
Test-Edit session, even when you cancel your edits
▪
Word-for-word change
▪
Downloading to RAM only of a stopped PACSystems CPU, even if the downloaded contents are
equal to the contents already on the nonvolatile storage
Setting bit 0 of input word 4 (address + 4) to a value of 1 enables SVC_REQ 57 despite the above
conditions.
6.33.8
Error Checking
When writing to nonvolatile storage, error checking is provided to ensure that logic and the
Hardware Configuration (HWC) in nonvolatile memory match the logic and HWC in PACSystems
RAM.
336
PACSystems* RX7i, RX3i and RSTi-EP CPU Programmer's Reference Manual
GFK-2950C
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