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12.9 8-bit Timer Interrupts
The 8-bit timer outputs interrupt requests to the interrupt controller (ITC) when the counter underflows.
To generate a timer underflow interrupt, the interrupt level and interrupt permission should be set using the ITC
registers.
Timer interrupt ITC register
The 8-bit timer ITC control bits are listed below.
Interrupt flag IIFT0
∗ IIFT0: 8-bit Timer Interrupt Flag in the Interrupt Flag (ITC_IFLG) Register (D8/0x4300)
Interrupt enable bit IIEN0
∗ IIEN0: 8-bit Timer Interrupt Enable Bit in the Interrupt Enable (ITC_EN) Register (D8/0x4302)
Interrupt level setting bit IILV0
∗ IILV0[2:0]: 8-bit Timer Interrupt Level Bits in the Internal Interrupt Level Setup (ITC_ILV0) Register 0
(D[2:0]/0x430e)
If an underflow occurs in the timer, the corresponding interrupt flag is set to 1.
If the interrupt enable bit corresponding to that interrupt flag is set to 1, the ITC sends an interrupt request to
the S1C17 core. To prohibit timer interrupts, set the interrupt enable bit to 0 beforehand. The interrupt flag will
be set to 1 by the timer underflow pulse regardless of the interrupt enable bit setting (i.e., even if set to 0).
The interrupt level setting bit sets the timer interrupt level (0 to 7).
The S1C17 core accepts interrupts when all of the following conditions are satisfied:
• The interrupt enable bit has been set to 1.
• The PSR (S1C17 core internal processor status register) IE (interrupt enable) bit has been set to 1.
• The timer interrupt has a higher interrupt level set than that set for the PSR IL (interrupt level).
• No other interrupt factors having higher precedence (e.g., NMI) are present.
For more information on these interrupt control registers and operations when interrupts occur, see "6 Interrupt
Controller (ITC)."
Interrupt vectors
The 8-bit timer interrupt vector numbers and vector addresses are listed below.
Vector number: 12 (0x0c)
Vector address: 0x8030
S1C17001 TECHNICAL MANUAL
EPSON
12 8-BIT TIMER (T8F)
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