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Contention between Buffer Register Write and Input Capture: If the input capture signal is
generated in the T2 state of a buffer write cycle, the buffer operation takes precedence and the
write to the buffer register is not performed.
Figure 10-55 shows the timing in this case.
ø
Address
Write signal
Input capture
signal
TCNT
TGR
Buffer
register
Figure 10-55 Contention between Buffer Register Write and Input Capture
Buffer register write cycle
T1
T2
Buffer register
address
N
M
N
M
383
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