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8.3.8
Chain Transfer
Setting the CHNE bit to 1 enables a number of data transfers to be performed consectutively in
response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data
transfers, can be set independently.
Figure 8-9 shows the memory map for chain transfer.
DTC vector
Register information
address
start address
In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the
end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt
source flag for the activation source is not affected.
204
Register information
Register information
Figure 8-9 Chain Transfer Memory Map
CHNE = 1
CHNE = 0
Source
Destination
Source
Destination
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