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6.2.2
Break Address Register B (BARB)
BARB is the channel B break address register. The bit configuration is the same as for BARA.
6.2.3
Break Control Register A (BCRA)
Bit
CMFA
Initial value
Read/Write
R/(W)*
Note:* Only a 0 may be written to this bit to clear the flag.
BCRA is an 8-bit readable/writable register that controls channel A PC breaks. BCRA (1) selects
the break condition bus master, (2) specifies bits subject to address comparison masking, and (3)
specifies whether the break condition is applied to an instruction fetch or a data access. It also
contains a condition match flag.
BCRA is initialized to H'00 by a reset and in hardware standby mode.
Bit 7—Condition Match Flag A (CMFA): Set to 1 when a break condition set for channel A is
satisfied. This flag is not cleared to 0.
Bit 7
CMFA
Description
0
[Clearing condition]
When 0 is written to CMFA after reading CMFA = 1
1
[Setting condition]
When a condition set for channel A is satisfied
Bit 6—CPU Cycle/DTC Cycle Select A (CDA): Selects the channel A break condition bus
master.
Bit 6
CDA
Description
0
PC break is performed when CPU is bus master
1
PC break is performed when CPU or DTC is bus master
132
7
6
5
CDA
BAMRA2
0
0
0
R/W
R/W
4
3
BAMRA1
BAMRA0
CSELA1
0
0
R/W
R/W
2
1
0
CSELA0
BIEA
0
0
0
R/W
R/W
R/W
(Initial value)
(Initial value)
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