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B•1•3
P3 - Altera's In System Programming (ISP)
This is a 10 pin generic 0.100" pitch header connector, providing In System Programming capabil-
ity for Altera CPLD devices made programmable logic on board. The pinout of P3 is shown in
TABLE B1-4. "P3 - ISP Connector - Interconnect Signals"
TABLE B1-4. P3 - ISP Connector - Interconnect Signals
Pin No.
Signal Name
1
TCK
2
GND
3
TDO
4
VCC
5
TMS
6
N.C.
7
N.C.
8
N.C.
9
TDI
10
GND
B•1•4
P4 - Host Interface Connector
This is a 36 pin two rows 0.100" pitch header connector. For more user's convenience each of the
Host Interface signals is present at the CPM The pinout of P4 is shown in
Interface Connector - Interconnect Signals"
TABLE B1-5. P4 - Host Interface Connector - Interconnect Signals
Pin No.
Signal Name
1
GND
2
B-90
Freescale Semiconductor, Inc.
Attribute
I
ISP Test port Clock. This clock shifts in / out data to / from the
programmable logic JTAG chain.
P
Digital GND. Main GND plane.
O
ISP Transmit Data Output. This the prog. logic's JTAG serial data
output driven by Falling edge of TCK.
P
Connect to 3.3V power supply bus for feeding an external
programmer logic.
I
ISP Test Mode Select. This signal qualified with TCK, changes
the state of the prog. logic JTAG machine.
-
Not Connected.
-
Not Connected.
-
Not Connected.
I
ISP Transmit Data In. This is the prog. logic's JTAG serial data
input, sampled by the MCS8101 on the rising edge of TCK.
P
Digital GND. Main GND plane.
below:
Attribute
P
Digital GND. Main GND plane.
MSC8101ADS RevB User's Manual
For More Information On This Product,
Go to: www.freescale.com
below:
Description
TABLE B1-5. "P4 - Host
Description
MOTOROLA
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