Table of Contents
Advertisement
TABLE 4-4. Memory Controller Initialization for 100(50)
Reg.
Device Type
MBMR
QFALC - 4ch. T1/E1
Read Access
Write Access
Exception Access
Normal Operation
a. Table values in parentheses reflect the lower frequency bus.
b. With Host Enable.
c. If additional SDRAM device U38SP will be assembled on the ADS (special requirement).
38
Freescale Semiconductor, Inc.
Operating Instructions
Init Value
Bus
[hex]
10015400
10015418
Buffered
PPC
1001543c
00015400
MSC8101ADS RevB User's Manual
For More Information On This Product,
Go to: www.freescale.com
a
MHz
Description
60x bus select, refresh disable, write to UPM
RAM, Read loop execute 5 times, first RAM
address.
60x bus select, refresh disable, write to UPM
RAM, Write loop execute 5 times, RAM address
begins at 18H.
RAM address begins at 0x3c.
Execute at 0x0.
MOTOROLA
Advertisement
Table of Contents
