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•
PPC Bus SDRAM Controller
•
GPCM (Flash, BCSR, ATM, Ext. Tools)
•
UPM (QFALC, Ext. Tools)
2)
Communication functions which include:
•
ATM SAR
•
Fast Ethernet controller.
•
TDMs for T1/E1 and CODEC support
•
UART for terminal or host computer connection.
The internal registers of the MPC must be programmed after Hard reset as described in the
following paragraphs. The addresses and programming values are in Hexadecimal base.
For better understanding the of the following initialization refer to the
4•5•1
System Initialization
Hard Reset Config. Word is programmed in Flash according to
ration Word" on page
Register
Init Value[hex]
RMR
0001
IMMR
14700000
SYPCR
FFFFFFC3
BCR
0000_0000
4•5•1•1
Memory Controller Registers Programming
The memory controller on the MSC8101ADS is initialized to 50/100 MHz operation. I.e., registers'
programming is based on 50/100 MHz timing calculation.
MOTOROLA
Freescale Semiconductor, Inc.
Operating Instructions
40.
TABLE 4-3. SIU Registers' Programming
Check-Stop Reset enabled.
Internal space begins from 0x1470_0000
Software watchdog timer count - FFFF, Bus-monitor timing FF, PPC Bus-monitor -
Enabled, Local Bus-monitor - Enabled, S/W watch-dog - disabled, S/W watch-dog
(if enabled) causes reset, S/W watch-dog (if enabled) - prescaled.
Single MSC8101, 0 wait-states on address tenure, 1-level Pipeline depth,
Extended transfer mode disabled for PCC & Local Buses, Odd parity for PPC &
Local Buses (not relevant for this application, External Master delay enabled,
Internal space responds as 64 bit slave for external master (not relevant for this
application).
MSC8101ADS RevB User's Manual
For More Information On This Product,
Go to: www.freescale.com
TABLE 5-2. "Hard Reset Configu-
Description
35
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