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(3) 2PULSE
Accumulation of charges Is started and ended through the trigger pulse input to the DC IN/SYNC terminal or
trigger signal input (LVDS) to the DIGITAL terminal, the vertical sync signal is reset and field images are
Trigger pulse level
: (Low Level): Less than 0.5V , (High Level): 3.4V to 5V
(DC IN/SYNC terminal)
Trigger pulse fetch timing
: Rising edge / Falling edge / Pulse width
selectable
■When the trigger pulse fetch timing is set to pulse width
Trigger pulse width
: More than 16.7ms(FLD/FRM setting: FLD)
More than 33.4ms(FLD/FRM setting :FRM)
Trigger pulse interval
: More than 16.7ms(FLD/FRM setting: FLD)
More than 33.4ms(FLD/FRM setting: FRM)
■When the trigger pulse fetch timing is set to rising edge or falling edge
Trigger pulse width
: More than 2 u s
Trigger pulse interval
: More than 16.7ms(FLD/FRM setting: FLD)
More than 33.4ms(FLD/FRM setting: FRM)
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