Table of Contents
Advertisement
Timing Analysis
Figure 2-10 lists the format specification for timing analysis. All of the
SCSI lines can be seen on the HP 1630D and HP 1631D analyzer, but the
Tuning Selector Switch on the HP 10343B must be used to see the Parity,
Select, or Reset line. Since the HP 1630A/G and HP 1631A Logic
Analyzers have only eight timing channels, only the Timing Data or Status
lines can be seen at one time with these analyzers. To look at the Status or
Data lines, you must manually move pod 1 of the logic analyzer between
connector C (Data) and connector D (Status) of the HP 10269A/B.
Table 2-2 lists the SCSI signal connections for each pod.
liiliilWIB! Format Specification
MSl4--IIJhfimai
Podl
Pod0
fictivity>
Labe 1
Pol
DflTH
[ + 3
PHASE
[ + ]
REQ
[ + ]
PICK
[ + ]
BSY
[ + ]
SWTCH
[ + ]
[ + ]
C-D
[ + ]
MSG
[+]
ATM
[ + ]
0 7.0
[. ******** ]
[.***....
.]
C.* .]
[.*.
.3
C.*. . :.3
[.*. . .
.3
[...*
.3
[. .*.
.3
[.*.
.3
[*.
.3
Figure 2-10. Format Specification for Timing
SCSI Bus Preprocessing
2-25
Advertisement
Table of Contents
