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LH75400/01/10/11 (Preliminary) User's Guide
23.1 ADC Features
The ADC has the following features:
• A 10-bit fully differential Successive Approximation Register (SAR) with integrated
sample/hold (see Section 23.1.4 for an explanation of the SAR architecture)
• An 8-channel multiplexer that routes user-selected inputs to the ADC in single-ended
and differential modes
• A 16-entry × 16-bit wide FIFO that holds the 10-bit ADC output
• Front bias-and-control network for touch screen interface and support functions, which
are compatible with industry-standard 4- and 5-wire touch-sensitive panels
• Touch-pressure sensing circuits
• Pen-down sensing circuit and interrupt generator
• Independently controlled voltage reference generator
• Conversion automation function to minimize controller interrupt overhead
• Brownout Detector.
23.1.1 Bias-and-Control Network
The bias-and-control network supports both 4- and 5-wire touch panels. Multiplexers on
the reference inputs enable connection in both single-ended and differential modes.
• In 4-wire operation, connection is to inputs X+, X-, Y+, and Y-. Pull HIGH and pull LOW
switches allow X and Y coordinate measurement in addition to pen-pressure sensing.
The Pen Interrupt line is also available via the Interrupt Masking/Enabling Register
(see Section 23.3.2.4).
• In 5-wire operation, panel connections are to UL, UR, LL, and LR inputs, and the sense
input is connected to WIPER. The Pen Interrupt line is also available in this mode.
NOTE: For pen-triggered interrupts, use the following procedure instead of using the WIPER's Pen Interrupt
23.1.2 Clock Generator
The ADC has a programmable measurement clock that is derived from the crystal oscilla-
tor, (nominally 14.7456 MHz). The clock drives the measurement sequencer and the suc-
cessive-approximation circuitry. Higher clock frequencies can allow faster measurement
throughput. Slower clock frequencies, on the other hand, can allow fewer clocks to settle
for a measurement and can reduce ADC power consumption. If the clock is too slow, the
sample-and-hold amplifier on the ADC input may drop before the measurement is com-
plete.
See Section 23.3.2.5 for clock-gating options and for information about programming the
available clock frequencies. See Chapter 24 for the maximum ADC clock frequency and
sample-and-hold amplifier time constant.
(PENIRQ) pull-up. Before checking the Pen Down state, use bias-and-control network bit [2] to short
the AN0 pin to VDDA_ADC. This discharges the capacitor formed by the Touch Screen and any
capacitance added to the AN0 pin. To generate a Pen Down Interrupt, connect AN4 to VSSA_ADC
using bit [8] of the bias-and-control network. Then connect the PENIRQ detector to AN0 using bit [12]
of the bias-and-control network.
Analog-to-Digital Converter/Brownout Detector
6/25/03
23-3
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