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Synchronous Serial Port
18.5.2.5 Clock Prescale Register
CPSR is the Clock Prescale Register. The CPSR Register specifies the division factor by
which the input HCLK should be internally divided before further use. The active bits used
in this register are Read/Write.
The value programmed into this register is a value from 1 to 127. This register defaults to
zero, but is doubled buffered and reads back ones after Reset.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:16
15:3
7:1
0
18-16
Table 18-11. CPSR Register
31
30
29
28
27
0
0
0
0
0
R
R
R
R
R
15
14
13
12
11
///
0
0
0
0
0
W
W
W
W
W
Table 18-12. CPSR Register Definitions
NAME
///
Reserved Writing to these bits has no effect. Reading returns 0.
RES
Reserved Write as 0. Unpredictable behavior when read.
Clock Prescale Divisor A number from 1 to 127, depending on the
CPSDVSR
frequency of HCLK.
RES
Reserved Returns zero on read operations.
LH75400/01/10/11 (Preliminary) User's Guide
26
25
24
23
22
///
0
0
0
0
R
R
R
R
R
10
9
8
7
0
0
0
0
W
W
W
RW
RW
0xFFFC6000 + 0x010
DESCRIPTION
6/17/03
21
20
19
18
0
0
0
0
0
R
R
R
R
6
5
4
3
2
CPSDVSR
0
0
0
0
0
RW
RW
RW
RW
17
16
0
0
R
R
1
0
///
0
0
RW
R
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