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General Purpose Input/Output
21.2.3.19 Port I Data Direction Register
PIDDR is the Port I Data Direction Register.
Bits set in PIDDR set the corresponding PI pin to be an output:
• Bit [7] controls pin 136 when the pin is configured as PI7. It does not control pin 136
when the pin is configured as LCDVD7.
• Bit [6] controls pin 137 when the pin is configured as PI6. It does not control pin 137
when the pin is configured as LCDVD6.
• Bit [5] controls pin 138 when the pin is configured as PI5. It does not control pin 138
when the pin is configured as LCDVD5.
• Bit [4] controls pin 139 when the pin is configured as PI4. It does not control pin 139
when the pin is configured as LCDVD4.
• Bit [3] controls pin 141 when the pin is configured as PI3. It does not control pin 141
when the pin is configured as LCDVD3.
• Bit [2] controls pin 142 when the pin is configured as PI2. It does not configure pin 142
when the pin is configured as LCDVD2.
• Bit [1] controls pin 143 when the pin is configured as PI1. It does not configure pin 143
when the pin is configured as LCDVD1.
• Bit [0] controls pin 144 when the pin is configured as PI0. It does not control pin 144
when the pin is configured as LCDVD0.
Clearing a bit configures the pin to be an input. A System Reset clears all bits.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:8
7:0
21-22
Table 21-39. PIDDR Register
31
30
29
28
27
0
0
0
0
R
R
R
R
15
14
13
12
11
///
0
0
0
0
R
R
R
R
Table 21-40. PIDDR Register Definitions
NAME
///
Reserved Writing to these bits has no effect. Reading returns 0.
Port I Output/Input
Port I Data Direction
Bits set = Port I output.
Bits cleared = Port I input.
LH75400/01/10/11 (Preliminary) User's Guide
26
25
24
23
///
0
0
0
0
0
R
R
R
R
R
10
9
8
7
0
0
0
0
0
R
R
R
R
RW
0xFFFDB000 + 0x08
6/17/03
22
21
20
19
0
0
0
0
R
R
R
R
6
5
4
3
Port I Data Direction
0
0
0
0
RW
RW
RW
RW
FUNCTION
18
17
16
0
0
0
R
R
R
2
1
0
0
0
0
RW
RW
RW
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