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No. 2D730-148E*O
h&it~lik
-----------
T--,--------------1
1 and T/R Switch
Hout/Lout
Transmrt
Pulse
1 Generation
TXCL
Synch
PECL
Clocks
64 Pairs
2
4
I
i
64
4
\
I
I
4
'\
b
TX/RX
(64)
I
I
64
I
TXPG
JTAG
1
TITRS
64
\
(4x16-CH)
2
AA
Transmit
Voltage
Digital
Control
Digital
Control
Power
Supplies
Echo
Booster
TC Bus
Biasing
Voltage
Power
Supplies
P5A
1 P5D
1 M2-AR
1 P3.3-D
I
,-------------,--+-----------------
1
1 Analog
Control
I , DC "Itage
4
, Ligital
Control
RCFEMRS
Echo
Booster
1
Biasing
Voltage
I
Digital
Control
+
RCFEREF
I
b
1 VCM
RCTRVMD
b
RCTRAAC
'
Differential
OP
I VMID
b
b
Amps
, VTGC
2,
\
2
D
RCTRTGC
VAAC
b
RCTREBB
\
'
Power
Supplies
I M14A
P5 AC
1 P32-AC
, M2-AC
I Power
Supplies
I P3.3-AR
I
M2-AR
Digital
Interface
I
I
I
I
EPLD
1
TC Bus
A
4
b
Buffered
TC Bus
L..
r . .
b
+
JTAG
v
TTL Synch
TTL Clocks
Transceivers
PECL
to TTL
4
I
~TEy
2
Synch
PECL
PECL
6
+
Buffers
\
'
I Power
Supplies
\4
P3.3D
\
\
b
1 P5D
PECL
Clocks
I
ZA-RXAR
w/op-amp
(64x1-ch)
4
TRRCS
.-------________
-I
Power
Supply
I
1
P5D
I
PSTRTXVO
Power
PSTRTXVI
'
Supplies
P5AQ
M2-OAQ
b
P3-3AQ
b
M14AQ
b
P5l -
P5A
b
1
-I
P3.3-AC
P3.3AR
b
M2-AC
b
M2
-
M14A
I
TXVOi
TXVI
I
I
TR functional block diagram for transmit pulse generation
4-12
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