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port J pin assignment (PJPAR), 26-18
port output data (PORTn), 26-8
port pin data/set data (PORTnP/SETn), 26-11
port QS pin assignment (PQSPAR), 26-21
port SD pin assignment (PSDPAR), 26-19
port TC pin assignment (PTCPAR), 26-22
port TD pin assignment (PTDPAR), 26-23
port UA pin assignment (PUAPAR), 26-24
2
I
C
address (I2ADR), 24-6
control (I2CR), 24-8
data I/O (I2DR), 24-10
frequency divider (I2FDR), 24-7
status (I2SR), 24-9
interrupt controller
interrupt
acknowledge
(IACKLPRn), 10-11
interrupt control (ICRnx), 10-11
interrupt
force
INTFRCLn), 10-9
interrupt pending high/low (IPRHn, IPRLn), 10-6
interrupt request level (IRLRn), 10-10
mask high/low (IMRHn, n), 10-8
JTAG
boundary scan, 31-6
bypass, 31-6
IDCODE, 31-5
instruction shift (IR), 31-5
JTAG_CFM_CLKDIV, 31-6
TEST_CTRL, 31-6
power management
low-power control (LPCR), 7-4
low-power interrupt control (LPICR), 7-2
programmable interrupt timers
control and status (PCSR), 19-4
count (PCNTR), 19-6
modulus (PMR), 19-5
QADC
control 2–0 (QACRn), 27-11–27-16
conversion command word (CCW), 27-26, 27-59
left-justified signed (LJSRR), 27-30
left-justified unsigned (LJURR), 27-30
module configuration (QADCMCR), 27-8
port data (PORTQA and PORTQB), 27-9
port QA and QB data direction (DDRQA,
DDRQB), 27-10
result word table, 27-62
right-justified unsigned result (RJURR), 27-29
status 0–1 (QASRn), 27-19, 27-26
successive approximation (SAR), 27-37
test (QADCTEST), 27-9
QSPI
address (QAR), 22-14
command RAM (QCRn), 22-15
Index-12
INDEX
level
and
priority
high/low
(INTFRCHn,
MCF5282 User's Manual
data (QDR), 22-14
delay (QDLYR), 22-11
interrupt (QIR), 22-13
mode (QMR), 22-10
wrap (QWR), 22-12
reset controller
control (RCR), 28-3
status (RSR), 28-4
SCM
bus master park (MPARK), 8-12
core reset status (CRSR), 8-6
core watchdog control (CWCR), 8-6
core watchdog service (CWSR), 8-9
grouped
peripheral
(GPACRn), 8-18
IPSBAR, 8-3
master privilege (MPR), 8-16
peripheral access control (PACRn), 8-16
RAMBAR, 2-8, 2-8, 5-2, 8-4
SDRAM controller
address and control 1–0 (DACRn), 15-6
control (DCR), 15-5
mask (DMRn), 15-8
mode register
initialization, 15-23
settings, 15-18
UART modules
auxiliary control (UACRn), 23-13
baud rate generator (UBG1n/UBG2n), 23-14
clock select (UCSRn), 23-8
command (UCRn), 23-9
input port (UIPn), 23-15
input port change (UIPCRn), 23-12
interrupt status/mask (UISRn/UIMRn), 23-13
mode 2–1 (UMRnn), 23-4–23-6
output port command (UOP1n/UOP0n), 23-15
receive buffers (URBn), 23-11
status (USRn), 23-7
transmit buffers (UTBn), 23-11
watchdog timer
control (WCR), 18-3
count (WCNTR), 18-5
modulus (WMR), 18-4
service (WSR), 18-5
Remote frames, 25-12
Remote loop-back, 23-26
Reset controller
block diagram, 28-2
control flow, 28-8
electrical characteristics
reset and configuration override timing, 33-18
features, 28-1
low-power modes, 7-10
memory map, 28-3
access
control
MOTOROLA
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