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Programming Model
31
Field
Reset
R/W
15
Field
Reset
R/W
Address
Figure 17-14. Physical Address Low Register (PALR)
Bits
31–0
17.5.4.12 Physical Address High Register (PAUR)
The PAUR is written by the user. This register contains the upper 16 bits (bytes 4 and 5) of
the 48-bit address used in the address recognition process to compare with the DA
(destination address) field of receive frames with an individual DA. In addition, this
register is used in bytes 4 and 5 of the 6-byte Source Address field when transmitting
PAUSE frames. Bits 15:0 of PAUR contain a constant type field (0x8808) used for
transmission of PAUSE frames. This register is not reset and bits 31:16 must be initialized
by the user.
31
Field
Reset
R/W
15
Field
Reset
R/W
Address
Figure 17-15. Physical Address High Register (PAUR)
17-36
Uninitialized
Uninitialized
IPSBAR + 0x10E4
Table 17-23. PALR Field Descriptions
Name
PADDR1
Bytes 0 (bits 31:24), 1 (bits 23:16), 2 (bits 15:8) and 3 (bits
7:0) of the 6-byte individual address to be used for exact
match, and the Source Address field in PAUSE frames.
Uninitialized
1000_1000_0000_1000
IPSBAR + 0x10E8
MCF5282 User's Manual
PADDR1
R/W
PADDR1
R/W
Description
PADDR2
R/W
TYPE
R
16
0
16
0
MOTOROLA
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