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Sony HAP-S1 Service Manual page 87

Hdd audio player system
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Pin No.
Pin Name
C9
RTC_XTALO
C10
GND24
C11
POR_B
C12
BOOT_MODE0
C13
SD3_DAT5
C14
SATA_REXT
C15
NANDF_CLE
C16
NANDF_CS1
C17
NANDF_D1
C18
NANDF_D7
C19
SD4_DAT5
C20
SD1_DAT1
C21
SD2_CLK
C22
RGMII_TD0
C23
RGMII_TX_CTL
C24
RGMII_RD0
C25
EIM_D16
D1
CSI_D1M
D2
CSI_D1P
D3
GND27
D4
CSI_REXT
D5
CLK2_P
D6
GND28
D7
CLK1_P
D8
GND29
D9
RTC_XTALI
D10
USB_H1_VBUS
D11
PMIC_ON_REQ
D12
ONOFF
D13
SD3_DAT4
D14
SD3_CLK
D15
SD3_RST
D16
NANDF_CS3
D17
NANDF_D3
SD4_DAT0,
D18, D19
SD4_DAT7
D20
SD1_CLK
D21
RGMII_TXC
D22
RGMII_RX_CTL
D23
RGMII_RD3
D24
EIM_D18
D25
EIM_D23
E1
CSI_D2M
E2
CSI_D2P
E3
CSI_D0P
E4
CSI_D0M
E5 to E7
GND30 to GND32
E8
NVCC_PLL_OUT
E9
USB_OTG_VBUS
E10
USB_H1_DP
E11
TAMPER
E12
TEST_MODE
E13
SD3_DAT6
E14
SD3_DAT0
E15
NANDF_WP_B
E16
SD4_CLK
E17
NANDF_D6
E18
SD4_DAT4
E19
SD1_DAT2
E20
SD2_DAT1
I/O
O
Real time clock output terminal (32.768 kHz)
-
Ground terminal
I
Reset signal input from reset signal generator and system controller
I
Boot mode setting terminal
-
Not used
-
Terminal for the impedance calibration
O
Update signal output to the system controller
O
Reset signal output terminal
I/O
Two-way data bus terminal
-
Not used
I/O
Two-way data bus with the fl ash memory
I/O
Two-way data bus terminal
-
Not used
O
RGMII transmit data output to the ethernet transceiver
O
RGMII transmit data enable signal output to the ethernet transceiver
I
RGMII receive data input from the ethernet transceiver
-
Not used
-
Not used
-
Not used
-
Ground terminal
-
Not used
-
Not used
-
Ground terminal
O
Clock signal (positive) output to the FPGA
-
Ground terminal
I
Real time clock input terminal (32.768 kHz)
I
Power supply of the USB interface for the WLAN/BT COMBO card
O
Not used
-
Not used
-
Not used
-
Not used
-
Not used
-
Not used
-
Not used
I/O
Two-way data bus with the fl ash memory
O
Clock signal output terminal
O
RGMII transmit clock signal output to the ethernet transceiver
I
RGMII receive data valid signal input from the ethernet transceiver
I
RGMII receive data input from the ethernet transceiver
-
Not used
I
Status signal input from the FPGA
-
Not used
-
Not used
-
Not used
-
Not used
-
Ground terminal
-
Power supply terminal for the PLL output
I
Power supply of the USB interface for the USB connector
I/O
Two-way USB data (positive) with the WLAN/BT COMBO card
I
Mode setting terminal
Fixed at "H"
I
Mode setting terminal
Not used
-
Not used
-
Not used
O
LED drive signal output terminal
O
Clock signal output to the fl ash memory
-
Not used
I/O
Two-way data bus with the fl ash memory
I/O
Two-way data bus terminal
-
Not used
Description
Fixed at "L"
"H": update
Not used
Not used
Not used
Not used
Not used
"H": LED on
Not used
HAP-S1
"L": reset
87
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