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source priorities 4-22
,
,
sources 4-19
4-20
B-8
table 4-18
table, memory map 4-20
trigger mode 4-20
vector 4-20
interrupt and mode control 2-9
interrupt conditions 5-2
interrupt control 2-9
Interrupt Control Register (ICR)
programming sheet B-24
Interrupt Mask (I) bits 4-13
Interrupt Priority Register Core (IPRC) 4-19
IRQD–IRQA Priority and Mode (IDL–IAL) 4-19
Interrupt Priority Register Peripherals (IPRP) 4-19
ESSI0 Interrupt Priority Level (S0L) 4-19
ESSI1 Interrupt Priority Level (S1L) 4-19
HI08 Interrupt Priority Level (HPL) 4-19
SCI Interrupt Priority Level (SCL) 4-19
Timer Interrupt Priority Level (TOL) 4-19
Interrupt Priority Register-Core (IPR-C)
programming sheet B-14
Interrupt Priority Register-Peripherals (IPR-P)
programming sheet B-15
interrupt routines
Host Interface (HI08) 6-8
Interrupt Service Routine (ISR) 7-9
interrupt trigger event 7-9
Interrupt Vector Register (IVR) 6-23
programming sheet B-25
,
Inverter (INV) bit 9-30
9-32
IRQD–IRQA Priority and Mode (IDL–IAL) bits 4-19
J
Joint Test Action Group (JTAG) 1-9
Test Acces Port(TAP) 1-5
L
Limit (L) bit 4-14
Loop Address register (LA) 1-8
Loop Counter register (LC) 1-8
M
M68HC11 SCI interface 8-16
manual conventions 1-2
mapping control registers 5-2
MC68000 family 6-29
MC68681 DUART 8-16
memory
allocation switching 3-2
configuration 3-5
Index-8
,
9-4
,
,
2-21
4-38
DSP56303 User's Manual
dynamic switching 3-5
expansion 3-1
external expansion port 1-10
maps 3-7
on-chip 1-9
Memory Expansion Port 1-5
memory map
internal I/O B-3
Memory Switch mode 3-2
X data Memory 3-3
X data memory 3-4
Memory Switch Mode (MS) bit 4-17
MODD, MODC, MODB, and MODA 8-8
mode control 2-9
Mode Register (MR) 4-10
Do Loop Flag (LF) 4-11
Double-Precision Multiply Mode (DM) 4-12
Interrupt Mask (I) 4-13
Scaling (S) Mode 4-13
Sixteen-Bit Compatibility (SC) mode 4-12
Mode Select (MOD) bit 7-21
move (MOVE, MOVEP) instructions 5-2
MOVEP instruction 6-13
Multidrop mode 8-2
,
multiplexed bus mode 2-2
Multiplication Factor (MF) bits 4-25
Multiplier-Accumulator (MAC) 1-6
N
Negative (N) bit 4-14
Network mode 7-8
non-multiplexed bus mode 2-2
O
,
off-chip memory 1-5
3-1
On-Chip Emulation (OnCE) module 1-5
,
on-chip memory 1-5
1-9
,
On-Demand mode 7-10
7-15
operating frequency 1-5
operating mode 4-2
Host Interface (HI08) 6-18
Operating Mode Register (OMR) 1-8
Address Attribute Priority Disable (APD) 4-16
Address Trace Enable (ATE) 4-16
Asynchronous Bus Arbitration Enable (ABE) 4-16
Bus Release Timing (BRT) 4-17
Cache Burst Mode Enable (BE) 4-17
Chip Operating Mode (MD–MA) 4-18
COM byte 4-15
Core-DMA Priority (CDP) 4-17
EOM byte 4-15
External Bus Disable (EBD) 4-18
,
,
6-4
6-17
6-20
,
6-4
,
,
1-9
2-21
,
4-15
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